Photonic A/D conversion using low-temperature-grown GaAs MSM switches integrated with Si-CMOS

By linking the unique capabilities of photonic devices with the signal processing power of electronics, photonically sampled analog-to-digital (A/D) conversion systems have demonstrated the potential for superior performance over all-electrical A/D conversion systems. We adopt a photonic A/D conversion scheme using low-temperature (LT)-grown GaAs metal-semiconductor-metal (MSM) photoconductive switches integrated with Si-CMOS A/D converters. The large bandwidth of the LT GaAs switches and the low timing jitter and short width of mode-locked laser pulses are combined to accurately sample input frequencies up to several tens of gigahertz. CMOS A/D converters perform back-end digitization, and time-interleaving is used to increase the total sampling rate of the system. In this paper, we outline the development of this system, from optimization of the LT GaAs material, speed and responsivity measurements of the switches, bandwidth and linearity characterization of the first-stage optoelectronic sample-and-hold, to integration of the switches with CMOS chips. As a final proof-of-principle demonstration, a two-channel system was fabricated with LT GaAs MSM switches flip-chip bonded to CMOS A/D converters. When operated at an aggregate sampling rate of 160 megasamples/s, the prototype system exhibits /spl sim/3.5 effective number of bits (ENOB) of resolution for input signals up to 40 GHz.     

A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling

GaAs photoconductive switches have been integrated with two parallel 4-bit CMOS analog-to-digital (A/D) converter channels to demonstrate the time-interleaved sampling of wideband signals. The picosecond sampling aperture provided by low-temperature-grown-GaAs metal-semiconductor-metal switches, in combination with low-jitter short-pulse lasers, enables the optically-triggered sampling of electrical signals with tens of gigahertz bandwidth at low to medium resolution. A pair of parallel sampling paths, one for sampling and the second for feedthrough cancellation, generate a differential held signal that is quantized by a low-input capacitance, high-speed flash A/D converter. Dynamic offset averaging is employed to improve converter linearity. An experimental time-interleaved two-channel A/D converter provides about 3.5 effective bits of resolution for inputs up to 40 GHz when tested at an optically-triggered sampling rate of 160 MHz. The sampling rate was limited by the available optical source. Each A/D converter channel operates up to a 640-MHz conversion rate, dissipates 70 mW of power, and occupies an area of 150 /spl mu/m /spl times/ 450 /spl mu/m in a 2.5-V, 0.25-/spl mu/m CMOS technology.