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We present a packet-by-packet contention resolution scheme that combines packet detection, optical space switching, and wavelength conversion performed in the optical domain by integrated optical switches. The packet detection circuit provides the control signals required to deflect and wavelength-convert the contending packets so that all the packets are forwarded to the same output without any collision or packet droppings. We demonstrate the compatibility of the scheme with both nonreturn-to-zero (NRZ) and return-to-zero (RZ) modulation formats by recording error-free operation for 10-Gb/s NRZ and 40-Gb/s RZ packet-mode traffic  相似文献   
2.
Recent advances in the all-optical signal processing domain report high-speed and nontrivial functionality directly implemented in the optical layer. These developments mean that the all- optical processing of packet headers has a future. In this article we address various important control plane issues that must be resolved when designing networks based on all-optical packet-switched nodes.  相似文献   
3.
We present a new scheme for all-optical contention detection and time-domain contention resolution of optical packets in label-switched routers that employ all-optical label recognition. The contention detection subsystem provides all the necessary control signals required to drive an optically controlled buffer which employs 1 times 2 optical switching elements and an optical fiber delay line. The state of the buffer is dynamically controlled on a per-packet basis with all the decisions and processing performed in the optical domain. Physical layer simulations show successful buffering and forwarding of 40-Gb/s optical packets with 2-dB power penalty  相似文献   
4.
The Information Society Technologies-all-optical LAbel SwApping employing optical logic Gates in NEtwork nodes (IST-LASAGNE) project aims at designing and implementing the first, modular, scalable, and truly all-optical photonic router capable of operating at 40 Gb/s. The results of the first project year are presented in this paper, with emphasis on the implementation of network node functionalities employing optical logic gates and optical flip-flops, as well as the definition of the network architecture and migration scenarios.  相似文献   
5.
Error-free operation of an all-optical wavelength converter at 160 Gbit/s based on a semiconductor optical amplifier and a silicon-on-insulator photonic circuit, consisting of two cascaded Mach-Zehnder delay interferometers, is demonstrated.  相似文献   
6.
A 40-Gb/s asynchronous self-routing network and node architecture that exploits bit and packet level optical signal processing to perform synchronization, forwarding, and switching in the optical domain is presented. Optical packets are self-routed on a hop-by-hop basis through the network by using stacked optical tags, each representing a specific optical node. Each tag contains necessary control signals for configuring the node-switching matrix and forwarding each packet to the appropriate outgoing link and onto the next hop. In order to investigate the feasibility of their approach physical-layer simulations are performed, modeling each optical subsystem of the node showing acceptable signal quality and end-to-end bit error rates. In the All-optical self-RouTer EMploying bIt and packet-level procesSing (ARTEMIS) control plane, a timed/delayed resource reservation-based signaling scheme is employed combined with a load-balancing feedback-based contention-avoidance mechanism that can guarantee a high performance in terms of blocking probability and end-to-end delay.  相似文献   
7.
Packet-format and network-traffic transparent optical signal processing   总被引:1,自引:0,他引:1  
In this paper, we demonstrate optical transparency in packet formatting and network traffic offered by all-optical switching devices. Exploiting the bitwise processing capabilities of these "optical transistors," simple optical circuits are designed verifying the independency to packet length, synchronization and packet-to-packet power fluctuations. Devices with these attributes are key elements for achieving network flexibility, fine granularity and efficient bandwidth-on-demand use. To this end, a header/payload separation circuit operating with IP-like packets, a clock and data recovery circuit handling asynchronous packets and a burst-mode receiver for bursty traffic are presented. These network subsystems can find application in future high capacity data-centric photonic packet switched networks.  相似文献   
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