Study of 18-cm long single-sided AC-coupled silicon microstripdetectors

The SSC GEM silicon Central Tracker design incorporated 18-cm long single-sided AC-coupled silicon microstrip ladders. Compared to the 12-cm long ladders considered in the preliminary stages of the tracker design, the 18-cm long ladders have the advantage of reduced cost, channel count and overall power consumption, and led to a simplified tracker assembly. However, such long ships also present the challenge of maintaining satisfactory performance. The increased capacitance and series resistance contribute to lower signal-to-noise ratios, longer time walk, higher power consumption per channel and increased probability of crosstalk to neighboring channels. In this paper, an accurate method to calculate the geometric capacitance of the AC-coupled microstrips is presented and the calculated results are compared with measurements, SPICE simulations are performed to predict the noise, the extent of interstrip capacitive coupling and the dispersion of the detector signal due to the finite series resistance of the metal strips and the long length of the detector. The influence of the preamplifier current and the shaping time on the signal and noise levels is also presented. The study concludes that the 18-cm long ladders can successfully satisfy the performance goals of the GEM silicon Central Tracker     

Adapting content for wireless Web services

Motorola Labs' Web-enabled museum system demonstrates how context-aware wireless Web services can adapt their content to a user's dynamic context.     

Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell

A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data recovery circuit uses select transitions for receive clock recovery. Bit-error rate less than 10/sup -15/ and power equal to 40 mW/Gb/s has been measured when operating over a 20-in backplane with two connectors at 10 Gb/s.     

Atomistic modeling and rational design of optothermal tweezers for targeted applications

Optical manipulation of micro/nanoscale objects is of importance in life sciences,colloidal science,and nanotechnology.Optothermal tweezers exhibit superior manipulation capability at low optical intensity.However,our implicit understanding of the working mechanism has limited the further applications and innovations of optothermal tweezers.Herein,we present an atomistic view of opto-thermo-electro-mechanic coupling in optothermal tweezers,which enables us to rationally design the tweezers for optimum performance in targeted applications.Specifically,we have revealed that the non-uniform temperature distribution induces water polarization and charge separation,which creates the thermoelectric field dominating the optothermal trapping.We further design experiments to systematically verify our atomistic simulations.Guided by our new model,we develop new types of optothermal tweezers of high performance using low-concentrated electrolytes.Moreover,we demonstrate the use of new tweezers in opto-thermophoretic separation of colloidal particles of the same size based on the difference in their surface charge,which has been challenging for conventional optical tweezers.With the atomistic understanding that enables the performance optimization and function expansion,optothermal tweezers will further their impacts.     

Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery

This paper describes an adaptively equalized, dual-mode (PAM2 one-tap DFE/PAM4) 0.13 /spl mu/m CMOS transceiver chip, and the techniques used to continuously adapt the link. Interestingly, with only minor modification the same hardware needed to implement a PAM4 system can be used to implement a PAM2 loop-unrolled single-tap decision-feedback equalization (DFE) receiver. Adaptive equalization using data-based update filtering allows continuous updates while minimizing the required sampler front-end hardware and significantly reduces the cost of implementation in multi-level signaling schemes. To allow the transmitter to adapt to the channel, the link uses common-mode signaling to create a back-channel communication path over the existing pair of wires. The design uses a three-level return-to- signaling scheme which allows the receiver to simultaneously extract voltage and timing references and minimize the required receiver hardware. The measured results indicate that this back-channel achieves reliable communication without noticeable impact on the forward link for back-channel data rates of up to 16 Mb/s and swings of 20-100 mV.