Fluorescent Brightener 28 Removal by Ozonation or Advanced Oxidation Processes (O3/H2O2)

The aim of this work is to study the reaction of ozone and combined ozone/hydrogen peroxide mixtures with the fluorescent brightener 28 in dilute aqueous solution using controlled experimental conditions. The kinetics were also evaluated under various experimental conditions. The main ozonation by-products have been identified by High Pressure Anionic Exchange Chromatography (HPAEC) and Gas Chromatography coupled with Mass Spectrometry (GC-MS) techniques and a reaction pathway is proposed. In order to confirm this mechanism, melamine and s-triazine have been treated under the same reaction conditions and their decomposition pathways were studied.     

Axiom-based ontology matching

Abstract: Managing multiple ontologies is now a core question in most of the applications that require semantic interoperability. The semantic web is surely the most significant application of this report: the current challenge is not to design, develop and deploy domain ontologies but to define semantic correspondences among multiple ontologies covering overlapping domains. In this paper, we introduce a new approach of ontology matching named axiom-based ontology matching. As this approach is founded on the use of axioms, it is mainly dedicated to heavyweight ontologies, but it can also be applied to lightweight ontologies as a complementary approach to the current techniques based on the analysis of natural language expressions, instances and/or taxonomical structures of ontologies. This new matching paradigm is defined in the context of the conceptual graphs model, where the projection (i.e. the main operator for reasoning with conceptual graphs which corresponds to homomorphism of graphs) is used as a means to semantically match the concepts and the relations of two ontologies through the explicit representation of the axioms in terms of conceptual graphs. We also introduce an ontology of representation, called MetaOCGL, dedicated to the reasoning of heavyweight ontologies at the meta-level.     

Energy Aware Algorithm and Implementation of SDR Oriented HSDPA Chip Level Equalizer

The flexibility and programmability of SDR come at the expense of reduced efficiency and increased energy consumption. This is usually considered as the penalty of SDR. However, the flexibility and programmability have great potentials for improving the system-wide efficiency if they are properly exploited. In this paper, we present a HSDPA chip equalizer that is explicitly designed for SDR implementations. The first SDR-specific feature of our work is the multi-mode operation based on heterogeneous algorithms. The proposed equalizer combines an optimized LMS variant (with subspace-aware extension) and an optimized SRI-RLS algorithm based on QRD. Instead of always applying the powerful SRI-RLS algorithm, the equalizer switches to simple LMS-variant when possible. With negligible BER degradation, the multi-mode operation can reduce 60% of the cycle-count on TI TMS320C6713 for 3GPP case 4 with 16QAM modulation. The proposed equalizer framework also incorporates a generic, robust and efficient scheme for equalization-length adaptation. The length-adaptation scheme can make very fast run-time decision based on an efficient policy-template, which is optimized with large training set at design time. We test 14 representative channel profiles specified in ITU-R M.1225, 3GPP TR 25.943 and 3GPP TS 25.101. Comparing to worst-case based design the length-adaptation achieves more than 10× cycle-count reductions for ten of the cases.     

Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments

In the context of future dynamic applications, systems will exhibit unpredictably varying platform resource requirements. To deal with this, they will not only need to be programmable in terms of instruction set processors, but also at least partial reconfigurability will be required. In this context, it is important for applications to optimally exploit the memory hierarchy under varying memory availability. This article presents a mapping strategy for wavelet-based applications: depending on the encountered conditions, it switches to different memory optimized instantations or localizations, permitting up to 51% energy gains in memory accesses. Systematic and parameterized mapping guidelines indicate which localization should be selected when, for varying algorithmic wavelet parameters. The results have been formalized and generalized to be applicable to more general wavelet-based applications.     

Energy Aware Signal Processing for Software Defined Radio Baseband Implementation

The fast pacing diversity and evolution of wireless communications require a wide variety of baseband implementations within a short time-to-market. Besides, the exponentially increased design complexity and design cost of deep sub-micron silicon highly desire the designs to be reused as much as possible. This yields an increasing demand for reconfigurable/ programmable baseband solutions. Implementing all baseband functionalities on programmable architectures, as foreseen in the tier-2 SDR, will become necessary in the future. However, the energy efficiency of SDR baseband platforms is a major concern. This brings a challenging gap that is continuously broadened by the exploding baseband complexity. We advocate a system level approach to bridge the gap. Specifically, we fully leverage the advantages (programmability) of SDR platforms to compensate its disadvantages (energy efficiency). Highly flexible and dynamic baseband signal processing algorithms are designed and implemented to exploit the abundant dynamics in the environment and the user requirement. Instead of always performing the best effort, the baseband can dynamically and autonomously adjust its work load to optimize the average energy consumption. In this paper, we will introduce such baseband signal processing techniques optimized for SDR implementations. The methodology and design steps will be presented together with 3 representative case studies in HSDPA, WiMAX and 3GPP LTE.     

Experience with Widening Based Equivalence Checking in Realistic Multimedia Systems

The application of loop and data transformations to array and loop intensive programs is crucial to obtain a good performance. Designers often apply these transformations manually or semi-automatically. For the class of static affine programs, automatic methods exist for proving the correctness of these transformations. Realistic multimedia systems, however, often contain constructs that fall outside of this class. We present an extension of a widening based approach to handle the most relevant of these constructs, viz. accesses to array slices, data dependent accesses and data dependent assignments, and report on some experiments with non-trivial applications.     

Efficient microcoded processor design for fixed rate DFT and FFT

Many Fourier transform applications have to operate at fixed sample rates in the low to medium range, especially in signal processing systems. Hence, in order to arrive at efficient implementations, hardware-sharing is required as in microcoded architectures. In this paper, very efficient application-specific realizations spanning a wide throughput range are proposed for both DFT and FFT algorithms. Novel single-cycle address computations are presented for the FFT to obtain these results. Trade-offs between the architectural alternatives are provided too. These designs have been used as test-vehicles for the architectural strategy in an automated synthesis tool-box tuned towards signal processing applications.This research has been sponsored in part within the context of the ESPRIT97 project by the EC and the industrial partners Philips, Siemens, BTMC/Alcatel and Silvar/Lisco.     

Address Generation Optimization for Embedded High-Performance Processors: A Survey

Nowadays embedded systems are growing at an impressive rate and provide more and more sophisticated applications characterized by having a complex array index manipulation and a large number of data accesses. Those applications require high performance specific computation that general purpose processors can not deliver at a reasonable energy consumption. Very long instruction word architectures seem a good solution providing enough computational performance at low power with the required programmability to speed up the time to market. Those architectures rely on compiler effort to exploit the available instruction and data parallelism to keep the data path busy all the time. With the density of transistors doubling each 18 months, more and more sophisticated architectures with a high number of computational resources running in parallel are emerging. With this increasing parallel computation, the access to data is becoming the main bottleneck that limits the available parallelism. To alleviate this problem, in current embedded architectures, a special unit works in parallel with the main computing elements to ensure efficient feed and storage of the data: the address generator unit, which comes in many flavors. Future architectures will have to deal with enormous memory bandwidth in distributed memories and the development of address generators units will be crucial for effective next generation of embedded processors where global trade-offs between reaction-time, bandwidth, energy and area must be achieved. This paper provides a survey of methods and techniques that optimize the address generation process for embedded systems, explaining current research trends and needs for future.

Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management

MATISSE is a design environment intended for developing systems characterized by a tight interaction between control and data-flow behavior, intensive data storage and transfer, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip hardware/software implementation. Matisse supports stepwise exploration and refinement of dynamic memory management, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for hardware synthesis, software compilation, and inter-processor communication synthesis. With this approach, specifications of embedded systems can be written in a high-level programming language using data abstraction. Application of MATISSE on telecom protocol processing systems in the ATM area shows significant improvements in area usage and power consumption.