Electrical test strategies for a wafer-level packaging technology

A wafer-level packaging (WLP) technology is under development that provides compliant electrical leads with a density as high as 12,000 per cm/sup 2/. The leads are batch processed while the integrated circuits are still in wafer form through a series of relatively simple photolithographic steps. After electrical testing, the wafers are diced and the integrated circuits (ICs) are ready for direct assembly to an interconnect substrate. Sufficient lateral and vertical compliance is provided by the leads to accommodate the nonplanarity encountered during assembly and the thermal mismatch between the IC and substrate during normal operation. The high density of compliant leads presents both challenges and opportunities for electrical testing. This paper first summarizes the process technology used to fabricate these high-density electrical contacts. Several potential test strategies are then introduced that may take advantage of these contacts.     

Low-cost test of embedded RF/analog/mixed-signal circuits in SOPs

Increasing levels of integration and high speeds of operation have made the problem of testing complex systems-on-packages (SOPs) very difficult. Testing packages with multigigahertz RF and optical components is even more difficult as external tester costs tend to escalate rapidly beyond 3 GHz. The extent of the problem can be gauged by the fact that test cost is approaching almost 40% of the total manufacturing cost of these packages. To alleviate test costs, various solutions relying on built-off test (BOT) and built-in test (BIT) of embedded high-speed components of SOPs have been developed. These migrate some of the external tester functions to the tester load board (BOT) and to the package and the die encapsulated in the package (BIT) in an "intelligent" manner. This paper provides a discussion of the emerging BOT and BIT schemes for embedded high-speed RF/analog/mixed-signal circuits in SOPs. The pros and cons of each scheme are discussed and preliminary available data on case studies are presented.     

Multiplexing ATE channels for production testing at 2.5 Gbps

We describe two versions of a multiplexing test system for multigigahertz devices. Our approach leverages test resources available in existing ATE, and achieves higher rates with added multiplexing logic. In the prototype, 32 high-speed differential-pair signals each support data at 2 Gbps to 2.5 Gbps. An updated system uses water cooling to better maintain the test electronics temperature. This system also has improved relays for better signal integrity, and better embedded calibration circuits to obtain stable operation at 2.5 Gbps. The production version is scalable to as many as 144 high-speed differential-pair signals. Integral to the design are embedded circuits that support automated, accurate timing calibration with 10-ps resolution.     

Source-synchronous testing of multilane PCI Express and HyperTransport buses

This article presents a modular approach for testing multigigahertz, multilane digital devices with source-synchronous I/O buses. This approach is suitable for integration with existing ATE and can provide more than 100 independent differential-pair signals. We describe a specific application with 32 lanes of PCI Express, running at 2.5 gigabits per second (Gbps) per lane, and 32 data channels of HyperTransport, at 1.6 Gbps per channel. The differential source-synchronous nature of these buses presents difficulties for traditional (single-ended, synchronous) ATE. We solve these problems by using true-differential driver and receiver test modules tailored for the specific I/O protocols. We satisfy a further requirement for jitter tolerance testing by incorporating a novel digitally synthesized jitter injection technique in the driver modules. The modular nature of our approach permits customization of the test system hardware and optimization for specific DUT test requirements.     

Transformation abrogates an early G1-phase arrest point required for specification of the Chinese hamster DHFR replication origin

The origin decision point (ODP) was originally identified as a distinct point during G1-phase when Chinese hamster ovary (CHO) cell nuclei experience a transition that is required for specific recognition of the dihydrofolate reductase (DHFR) origin locus by Xenopus egg extracts. Passage of cells through the ODP requires a mitogen-independent protein kinase that is activated prior to restriction point control. Here we show that inhibition of an early G1-phase protein kinase pathway by the addition of 2-aminopurine (2-AP) prior to the ODP arrests CHO cells in G1-phase. Transformation with simian virus 40 (SV40) abrogated this arrest point, resulting in the entry of cultured cells into S-phase in the presence of 2-AP and a disruption of the normal pattern of initiation sites at the DHFR locus. Cells treated with 2-AP after the ODP initiated replication specifically within the DHFR origin locus. Transient exposure of transformed cells to 2-AP during the ODP transition also disrupted origin choice, whereas non-transformed cells arrested in G1-phase and then passed through a delayed ODP after removal of 2-AP from the medium. We conclude that mammalian cells have many potential sites at which they can initiate replication. Normally, events occurring during the early G1-phase ODP transition determine which of these sites will be the preferred initiation site. However, if chromatin is exposed to S-phase-promoting factors prior to this transition, mammalian cells, like Xenopus and Drosophila embryos, can initiate replication without origin specification.     

Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic

This paper demonstrates the signal performance obtained by combining data from two 10 Gbps SiGe serializers using a very high-speed, low-jitter InP exclusive-OR gate. The technique has been used in the past for lower-speed (i.e. ≤12.8 Gbps) applications. However, success at higher speeds depends upon tight control of timing and signal integrity. Relatively low-cost (off-the-shelf) components are used so that the method can be applied to test scenarios requiring many high-speed channels. Analysis of the demonstration circuit performance reveals the challenges, capabilities, and limitations of the method. A Development Platform is also described that facilitates individual module characterization and integration of multiple modules to form customized test systems.     

Bit-parallel message exchange and data recovery in optical packet switched interconnection networks

Multiwavelength optical messages encoded in a bit-parallel fashion are successfully routed through five switching nodes of a 12-port optical packet switching interconnection network. The data payloads are entirely recovered and processed at the destination node using an embedded clock signal with a measured clock-to-data skew tolerance window of 150 ps.     

Extending a DWDM Optical Network Test System to 12 Gbps x4 Channels

A “Development Platform” for prototyping new multi-GHz ATE has recently been introduced (Keezer et al. 2009). The first application was a multi-channel test system for characterizing an optical network switch operating at 2.5 Gbps per channel (Keezer et al. 2009, 2010). Nine transmitter channels (TX) and nine receivers (RX) were used to test the Dense Wavelength Division Multiplexing (DWDM) switching network. This present paper incorporates elements from the prototype designs into full-feature test modules targeting applications between 2.5 Gbps and 24.0 Gbps per channel. Specifically, the optical test system is extended for burst-mode 12 Gbps DWDM packets (more than 4-times the rate of the original system). Using 8 TX channels, an aggregate data rate of 96 Gbps is achieved. Alternatively, some modules can be configured to double the channel-count (up to 18) while operating at the lower 2.5 Gbps rate (45 Gbps aggregate rate). Lower rates permit use of lower-cost optical components. Two new modules are described with testability features such as: (1) support for “loopback” testing of DUT output-to-inputs, (2) DC electrical tests, (3) 2-to-1 multiplexing up to 24 Gbps, (4) ATE self-test/calibration loopback paths. Recently multiple Development Platforms have been constructed that can operate either independently or synchronized using very low-jitter (~1 ps RMS) clock distribution paths.