A novel SONOS-type flash device with stacked charge trapping layer

Although enhancement in electrical properties of flash devices with HfO₂ charge trapping layer has been reported, there are serious problems in retention characteristics. In this work, a novel SONOS-type flash device with TaN/Al₂O₃/HfO₂/Si₃N₄/SiO₂/Si structure is presented. Experimental results show that the program/erase speeds of the proposed devices can be enhanced by over one thousand times and the retention characteristic is improved as well.     

Novel SONOS-Type Nonvolatile Memory Device With Optimal Al Doping in HfAlO Charge-Trapping Layer

Operation properties of polysilicon-oxide-nitride-oxide-silicon-type Flash device with HfAlO charge-trapping layer having various Al contents were investigated in this letter. Satisfactory performance in terms of operation speed, retention, and program/erase endurance of the Flash device is achieved with the optimal Al content of 18%-28% in the HfAlO trapping layer. In addition, high-speed operation can be attained with the combination of channel-hot-electron-injection programming and band-to-band hot hole erasing for NOR architecture applications.     

Photo-response of a nanopore device with a single embedded ZnO nanoparticle

The photo-response of a ZnO nanoparticle embedded in a nanopore made on a silicon nitride membrane is investigated. The ZnO nanoparticle is manipulated onto the nanopore and sandwiched between aluminum contact electrodes from both the top and bottom. The asymmetric device structure facilitates current-voltage rectification that enables photovoltaic capacity. Under illumination, the device shows open-circuit voltage as well as short-circuit current. The fill factor is found to increase at low temperatures and reaches 48.6% at 100?K. The nanopore structure and the manipulation technique provide a solid platform for exploring the electrical properties of single nanoparticles.     

Characterization of TiOxNy nanoparticles embedded in HfOxNy as charge trapping nodes for nonvolatile memory device applications

Silicon-oxide–nitride-oxide–silicon devices with nanoparticles (NPs) as charge trapping nodes (CTNs) are important to provide enhanced performance for nonvolatile memory devices. To study these topics, the TiO_xN_y metal oxide NPs embedded in the HfO_xN_y high-k dielectric as CTNs of the nonvolatile memory devices were investigated via the thermal synthesis using Ti thin-film oxidized in the mixed O₂/N₂ ambient. Well-isolated TiO_xN_y NPs with a diameter of 5–20 nm, a surface density of ～3 × 10¹¹ cm^?2, and a charge trap density of around 2.33 × 10¹² cm^?2 were demonstrated. The writing characteristic measurements illustrate that the memory effect is mainly due to the hole trapping.     

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.     

Thermal stability of Hf/sub x/Ta/sub y/N metal gate electrodes for advanced MOS devices

In this letter, the composition effects of hafnium (Hf) and tantalum (Ta) in Hf/sub x/Ta/sub y/N metal gate on the thermal stability of MOS devices were investigated. The work function of the Hf/sub x/Ta/sub y/N metal gate can reach a value of /spl sim/4.6 eV (midgap of silicon) by suitably adjusting the Hf and Ta compositions. In addition, with a small amount of Hf incorporated into a TaN metal gate, excellent thermal stability of electrical properties, including the work function, the equivalent oxide thickness, interface trap density and defect generation rate characteristics, can be achieved after a post-metal anneal up to 950/spl deg/C for 45 s. Experimental results indicate that Ta-rich Hf/sub x/Ta/sub y/N is a promising metal gate for advanced MOS devices.     

Plasma charging damage on MOS devices with gate insulator ofhigh-dielectric constant material

Plasma charging effects on the gate insulator of high-dielectric constant (k) material in MOS devices deserve to be investigated because of different trap-assisted conduction mechanisms. Plasma-induced degradation in gate-leakage current and time to breakdown is clearly observed in this work. MOS device with Si₃N₄ film seems to have smaller degradation of gate-leakage current while it suffers shorter time to breakdown as compared to Ta₂O₅ samples. For devices with Ta₂O₅ film, a larger physical thickness suffers more reliability degradation from plasma charging damage because of the richer traps. Thus, a smaller physical thickness of high-k dielectric film is favorable for sub-micron MOS devices of ULSI application     

Characterization of CoxNiyO hybrid metal oxide nanoparticles as charge trapping nodes in nonvolatile memory devices

The Co_xNi_yO hybrid metal oxide nanoparticles (HMONs) embedded in the HfO_xN_y high-k dielectric as charge trapping nodes of the nonvolatile memory devices have been formed via the chemical vapor deposition using the Co/Ni acetate calcined and reduced in the Ar/NH₃ ambient. A charge trap density of 8.96 × 10¹¹ cm^?2 and a flatband voltage shift of 500 mV were estimated by the appearance of the hysteresis in the capacitance–voltage (C–V) measurements during the ±5 V sweep. Scanning electron microscopy image displays that the Co_xNi_yO HMONs with a diameter of ～10–20 nm and a surface density of ～1 × 10¹⁰ cm^?2 were obtained. The mechanism related to the writing characteristics are mainly resulted from the holes trapping. Compared with those devices with the Co_xNi_yO HMONs formed by the dip-coated technique, memory devices with the Co_xNi_yO HMONs fabricated by the drop-coated technique show improved surface properties between the Co_xNi_yO HMONs and the HfON as well as electrical characteristics.     

Improvement of hot-carrier and radiation hardnesses inmetal-oxide-nitride-oxide semiconductor devices byirradiation-then-anneal treatments

The hardnesses of hot-carrier and radiation of metal-oxide nitride-oxide semiconductor (MONOS) devices can be improved by the irradiation-then-anneal (ITA) treatments. Each treatment includes an irradiation of Co-60 with a total dose of 1M rads(SiO₂) and an anneal in N₂ at 400°C for 10 min successively. This improvement can be explained by the release of SiO₂/Si interfacial strain     

Characteristics and thermal stability of MOS devices with MoN/TiN and TiN/MoN metal gate stacks

Metal gate with high work function is the key issue for MOS device. The influences of MoN metal gate with TiN layer above or below and various post metal annealing (PMA) treatments were studied in this work. Experimental results show that metal gate stack with TiN under MoN film (i.e., MoN/TiN sample) exhibits better electrical characteristics on gate leakage current, stress-induced flat-band voltage shift, and stress-induced leakage current and thermal stability despite a little lower work function. Thus MoN/TiN metal gate is promising for p-channel MOS device applications.