A new fast motion estimation algorithm using fast mode decision for high-efficiency video coding standard

High-efficiency video coding is the latest standardization effort of the International Organization for Standardization and the International Telecommunication Union. This new standard adopts an exhaustive algorithm of decision based on a recursive quad-tree structured coding unit, prediction unit, and transform unit. Consequently, an important coding efficiency may be achieved. However, a significant computational complexity is resulted. To speed up the encoding process, efficient algorithms based on fast mode decision and optimized motion estimation were adopted in this paper. The aim was to reduce the complexity of the motion estimation algorithm by modifying its search pattern. Then, it was combined with a new fast mode decision algorithm to further improve the coding efficiency. Experimental results show a significant speedup in terms of encoding time and bit-rate saving with tolerable quality degradation. In fact, the proposed algorithm permits a main reduction that can reach up to 75 % in encoding time. This improvement is accompanied with an average PSNR loss of 0.12 dB and a decrease by 0.5 % in terms of bit-rate.     

A novel architecture design for VLSI implementation of integer DCT in HEVC standard

This paper presents novel hardware of a unified architecture to compute the 4?×?4, 8?×?8, 16?×?16 and 32?×?32 efficient two dimensional (2-D) integer DCT using one block 1-D DCT for the HEVC standard with less complexity and material design. As HEVC large transforms suffer from the huge number of computations especially multiplications, this paper presents a proposition of a modified algorithm reducing the computational complexity. The goal is to ensure the maximum circuit reuse during the computation while keeping the same quality of encoded videos. The hardware architecture is described in VHDL language and synthesized on Altera FPGA. The hardware architecture throughput reaches a processing rate up to 52 million of pixels per second at 90 MHz frequency clock. An IP core is presented using the embedded video system on a programmable chip (SoPC) for implementation and validation of the proposed design. Finally, the proposed architecture has significant advantages in terms of hardware cost and improved performance compared to related work existing in the literature. This architecture can be used in ultra-high definition real-time TV coding (UHD) applications.

     

FPGA architecture of the LDPS Motion Estimation for H.264/AVC Video Coding

Motion estimation is a highly computational demanding operation during video compression process and significantly affects the output quality of an encoded sequence. Special hardware architectures are required to achieve real-time compression performance. Many fast search block matching motion estimation (BMME) algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose three new hardware architectures of fast search block matching motion estimation algorithm using Line Diamond Parallel Search (LDPS) for H.264/AVC video coding system. These architectures use pipeline and parallel processing techniques and present minimum latency, maximum throughput and full utilization of hardware resources. The VHDL code has been tested and can work at high frequency in a Xilinx Virtex-5 FPGA circuit for the three proposed architectures.     

Differential evolution for solving multi-mode resource-constrained project scheduling problems

In this paper we consider the resource-constrained project scheduling problem with multiple execution modes for each activity and minimization of the makespan. To solve this problem, we propose a differential evolution (DE) algorithm. We focus on the performance of this algorithm to solve the problem within small time per activity. Finally, we present the results of our thorough computational study. Results obtained on six classes of test problems and comparison with other algorithms from the literature show that our algorithm gives better solutions.     

Decentralized collaborative business process execution using blockchain

World Wide Web - Blockchain technology enables several untrustworthy parties to execute inter-organizational business processes in a tamper-proof manner. Existing approaches are based on smart...     

A Survey on Efficient Power Consumption in Adaptive Wireless Sensor Networks

The paper aims to give an extensive overview of the energy constraints in Wireless Sensor Networks and the power management strategies used in the literature as power efficiency is considered as the most challenging issue in WSNs. The paper opted for an investigative study of the adaptive systems that represent efficient solutions to deal with environmental and context changes in wireless sensor Networks. It provides thorough insights about how change has brought about the use of adaptive systems in WSNs. It proposes a new adaptation technique inspired from combining adaptation in different layers and can be more efficient and performing. This paper fulfills an identified need to study reconfigurable systems to achieve power efficiency, as a sensor node is power constrained.     

A hybrid algorithm for the cyclic hoist scheduling problem with two transportation resources

In automated electroplating lines, computer-controlled hoists are used to transfer parts from a processing resource to another one. Products are mounted into carriers and immersed sequentially in a series of tanks following a given sequence.     

Aggregate planning through the imprecise goal programming model: integration of the manager's preferences

Aggregate planning involves planning the best quantity to be produced during time periods in the medium‐range horizon at the lowest cost. Usually, the production manager seeks a plan that simultaneously optimizes several incommensurable and conflicting objectives, such as total cost, level of inventories, level of customer service, fluctuation in workforce, and utilization level of the physical facility and equipment. The goal programming (GP) model is one of the best known multi‐objective programming models that considers simultaneously several conflicting objectives to select the most satisfactory solution among a set of feasible solutions. In the production planning problem, the goals and the technological parameters are naturally imprecise. Moreover, the existing GP formulations developed in industrial engineering and aggregate production planning do not explicitly incorporate the manager's preferences. The aim of this paper is to develop a GP formulation within an imprecise environment where the concept of satisfaction function will be utilized to explicitly introduce the manager's preferences into the aggregate planning model.     

Hardware implementation and validation of the fast variable block size motion estimation architecture for H.264/AVC

Block matching motion estimation is the heart of video coding system. It leads to a high compression ratio, whereas it is time consuming and calculation intensive. Many fast search block matching motion estimation algorithms have been developed in order to minimize search positions and speed up computation but they do not take into account how they can be effectively implemented by hardware. In this paper, we propose an efficient hardware architecture of the fast line diamond parallel search (LDPS) algorithm with variable block size motion estimation (VBSME) for H.264/AVC video coding system. The design is described in VHDL language, synthesized to Altera Stratix III FPGA and to TSMC 0.18 μm standard-cells. The throughput of the hardware architecture reaches a processing rate up to 78 millions of pixels per second at 83.5 MHz frequency clock and uses only 28 kgates when mapped to standard-cells. Finally, a system on a programmable chip (SoPC) implementation and validation of the proposed design as an IP core is presented using the embedded video system.