Technologies for Ultradynamic Voltage Scaling

Energy efficiency of electronic circuits is a critical concern in a wide range of applications from mobile multimedia to biomedical monitoring. An added challenge is that many of these applications have dynamic workloads. To reduce the energy consumption under these variable computation requirements, the underlying circuits must function efficiently over a wide range of supply voltages. This paper presents voltage-scalable circuits such as logic cells, SRAMs, ADCs, and dc–dc converters. Using these circuits as building blocks, two different applications are highlighted. First, we describe an H.264/AVC video decoder that efficiently scales between QCIF and 1080p resolutions, using a supply voltage varying from 0.5 V to 0.85 V. Second, we describe a 0.3 V 16-bit microcontroller with on-chip SRAM, where the supply voltage is generated efficiently by an integrated dc–dc converter.      

An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Bias-Flip Rectifier and Shared Inductor

Harvesting ambient vibration energy through piezoelectric means is a popular energy harvesting technique which can potentially supply 10-100's of ?W of available power. One of the main limitations of existing piezoelectric harvesters is in their interface circuitry. In this paper, a bias-flip rectifier circuit that can improve the power extraction capability from piezoelectric harvesters over conventional full-bridge rectifiers and voltage doublers by greater than 4X is implemented in a 0.35 ?m CMOS process. An efficient control circuit to regulate the output voltage of the rectifier and recharge a storage capacitor is presented. The inductor used within the bias-flip rectifier is shared efficiently with a multitude of switching DC-DC converters within the system reducing the overall component count.     

Dipstick enzyme immunoassay for rinderpest antibody in cattle

A dipstick enzyme immunoassay (ELISA) has been standardized for the detection of rinderpest antibodies. One hundred and thirty bovine serum samples were analysed by the dipstick ELISA method and the results compared with the conventional plate ELISA method. The sensitivity was found to be similar in both methods. The dipstick ELISA does not require expensive micro-plates and an ELISA reader, and is recommended for use in field laboratories where the qualitative detection of rinderpest antibodies is required.     

Characterization of leptospiral serovars by randomly amplified polymorphic DNA fingerprinting

Randomly amplified polymorphic DNA (RAPD) fingerprinting of 14 laboratory strains of leptospiral serovars (serovars australis, autumnalis, ballum, bataviae, canicola, grippotyphosa, hardjoprajitno, hebdomadis, icterohaemorrhagiae, javanica, pomona, pyrogenes, panama, and tarassovi) was carried out by using a pair of primers. Each serovar had a unique and distinct fingerprint pattern. DNAs of other bacterial species, including Escherichia coli, Pasteurella multocida, Salmonella spp., Pseudomonas spp., and Klebsiella spp., did not show any amplification. RAPD fingerprinting was found to be a rapid and sensitive method for serovar identification when it was compared to DNA restriction enzyme analysis, which produced a larger number of bands that made it more difficult to compare serovars.     

Analysis of internal short-circuit in a lithium ion cell

An electrochemical thermal model was developed to study the internal short-circuit behavior of a lithium ion cell. The model was used to understand several experimental observations: several short-circuit scenarios possible in a lithium ion cell were simulated and the power generated from each case was calculated. Influence of parameters like the SOC and initial temperature of the cell was studied.Experiments were carried out to verify the predictions made using the model. Some pointers are provided towards design of a safer cell.     

Accurate and efficient processor performance prediction via regression tree based modeling

Computer architects usually evaluate new designs using cycle-accurate processor simulation. This approach provides a detailed insight into processor performance, power consumption and complexity. However, only configurations in a subspace can be simulated in practice due to long simulation time and limited resource, leading to suboptimal conclusions which might not be applied to a larger design space. In this paper, we propose a performance prediction approach which employs state-of-the-art techniques from experiment design, machine learning and data mining. According to our experiments on single and multi-core processors, our prediction model generates highly accurate estimations for unsampled points in the design space and show the robustness for the worst-case prediction. Moreover, the model provides quantitative interpretation tools that help investigators to efficiently tune design parameters and remove performance bottlenecks.     

A 65 nm Sub-$V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter

Aggressive supply voltage scaling to below the device threshold voltage provides significant energy and leakage power reduction in logic and SRAM circuits. Consequently, it is a compelling strategy for energy-constrained systems with relaxed performance requirements. However, effects of process variation become more prominent at low voltages, particularly in deeply scaled technologies. This paper presents a 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV. A 16-bit microcontroller core is designed with a custom sub-threshold cell library and timing methodology to address output voltage failures and propagation delays in logic gates. A 128 kb SRAM employs an 8 T bit-cell to ensure read stability, and peripheral assist circuitry to allow sub-Vt reading and writing. The logic and SRAM function in the range of 300 mV to 600 mV, consume 27.2 pJ/cycle at the optimal V _DD of 500 mV, and 1 muW standby power at 300 mV. To supply variable voltages at these low power levels, a switched capacitor DC-DC converter is integrated on-chip and achieves above 75% efficiency while delivering between 10 muW to 250 muW of load power.     

Effect of oxide additions on the properties of plasma-sprayed Y-Ba-Cu-O coatings

Plasma-spraying is a potential technique for forming flexible tapes from the brittle highT _c oxides. It is possible to obtain superconducting YBa₂Cu₃O _x coatings by a suitable heat-treatment after spraying. In an effort to improve the critical current densities of the coatings, the effect of additions of Ag₂O, Bi₂O₃ and SnO₂ to the YBa₂Cu₃O _x powder used for spraying was studied. The maximumJ _c value of 75 A/cm² was obtained for the sample doped with 5% SnO₂.     

IPv6 Protocol Analyzer

With the emerging of next generation Intemet protocol (IPv6), it is expected to replace the current version of Internet protocol (IPv4) that will be exhausted in the near future. Besides providing adequate address space, some other new features are included into the new 128 bits of IP such as IP auto configuration, quality of service, simple routing capability, security, mobility and multicasting. The current protocol analyzer will not be able to handle IPv6 packets. This paper will focus on developing protocol analyzer that decodes IPv6 packet. IPv6 protocol analyzer is an application module,which is able to decode the IPv6 packet and provide detail breakdown of the construction of the packet. It has to understand the detail construction of the IPv6, and provide a high level abstraction of bits and bytes of the IPv6 packet.Thus it increases network administrators' understanding of a network protocol,helps he/she in solving protocol related problem in a IPv6 network environment.