Minimizing FPGA interconnect delays

Optimizing FPGA routing architectures for speed performance also involves improving the CAD tools for mapping circuits. We provide a detailed example of how to design FPGA architectures by examining several important issues associated with interconnect resources for FPGAs that use SRAM programming technology. Our experiments examine two important metrics: the speed performance of implemented circuits and the effective use of available interconnect resources. The goal is to improve upon FPGA speed performance by decreasing delays associated with the interconnect. Our results are most directly applicable to FPGA architectures similar in style to the Xilinx XC4000 series. However, some significant results are of a more general nature and perhaps applicable to other styles of FPGAs as well. In addition to routing architectures, we address the CAD tools that allocate these routing resources to implement circuits     

Scalable cache consistency for hierarchically structured multiprocessors

This paper presents a new cache consistency scheme for hierarchically structured shared-memory multiprocessors. The scheme is simple, fast and efficient, and it does not require a large amount of state information to be maintained. The scheme exploits the broadcast capability of these systems, but limits the extent of the broadcasts by means of a novel filtering mechanism. As a specific example, it is shown how the proposed cache consistency scheme can be implemented on the Hector multiprocessor architecture. Using trace-driven simulations, we demonstrate that the scheme is scalable and performs well for common applications.     

Floating redundancy in digital systems

The traditional styles of redundancy such as triple modular redundancy (TMR) use exact functional duplicates to provide increased reliability [NE63]. This need not be the case; a system may be designed using floating redundancy. Floating redundancy improves reliability by using a floating spare that may perform as several module types. The adjective “floating” is used to describe this ability to function as two or more types.This paper outlines some of the results of a study of floating redundancy.     

Using active components to perform voltage division indigital-to-analog conversion

The design of a voltage-mode digital-to-analog (D/A) converter using only fabrication steps required by MOSFETs is described. The converter is implemented using a basic-circuit-building block called the three-input amplifier (TIAMP), which can perform voltage addition and voltage division by 2 without using any passive component. The technique has been used to implement a 12 bit D/A converter for which five samples were tested with accuracies ranging from 6 to 10 bits. Accuracy is limited in the present design by the relatively small sizes chosen for the input transistors. The maximum conversion rate of the present prototypes has been measured to be approximately 1 MHz with a static power dissipation of 50 mW     

Key compression using segment strings

The paper presents a method for one-probe accessing of records in static files. It compresses the record keys to the size of the required addresses. Unique addresses are produced, having the same order as the keys. A major advantage of the method is considerable reduction in the RAM storage, in comparison with the standard key-index methods.     

FERMTOR: A Tunable Multiprocessor Architecture

Multiprocessing can be cost-effective when a general-purpose system is adaptable to specific uses.     

Microcomputer interfacing module

The design of a microcomputer is presented, which provides a standard and versatile module for computer interfacing.     

The memory/logic interface in FPGAs with large embedded memoryarrays

As the capacities of field-programmable gate arrays (FPGAs) grow, they will be used to implement much larger circuits than ever before. These larger circuits often require significant amounts of storage. In order to address these storage requirements, FPGAs with large embedded memory arrays are now being developed by several vendors. One of the crucial components of an FPGA with on-chip memory is the routing structure between the memory arrays and logic resources. If this memory/logic interface is not flexible enough, many circuits will be unroutable, while if it is too flexible, it will be slower and consume more chip area than is necessary. In this paper, we show that an interconnect in which each memory pin can connect to between four and seven logic routing tracks is best in terms of both area and speed. We also show that by adding switches to support nets that connect multiple memory arrays, we can reduce the memory access time by up to 25% and improve the routability slightly     

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.