Materials study of silicon-on-lnsulator material by TEM

Silicon-on-insulator (SOI) technology addresses the need for many different device applications, such as radiation tolerant devices, high voltage, and three-dimensional circuitry applications. Isolated silicon epitaxy (ISE) is a commercialised process which results in excellent SOI material quality with proven results, having overcome most of the obstacles of other processes, although only having reduced, not eliminated, threading dislocations. The remaining isolated dislocations have been examined in detail by transmission electron microscopy (TEM). These have been diagnosed as normal lattice dislocations, with no faults or twins in the material. The nature, source, and behavior of the remaining dislocations is discussed.     

Micromechanical switches fabricated using nickel surfacemicromachining

Micromechanical switches have been fabricated in electroplated nickel using a four-level surface micromachining process. The simplest devices are configured with three terminals, a source, a drain, and a gate and are 30 μm wide, 1 μm thick, and 65 μm long. A voltage applied between the gate and source closes the switch, connecting the source to the drain. Devices switch more than 10⁹ cycles before failure and exhibit long-lifetime hot switching currents up to 5 mA. The initial contact resistance is less than 50 mΩ. The breakdown (stand-off) voltage between the source and the drain is greater than 100 V and the off-current is less than 20 fA at 100 V     

Creating 3D circuits using transferred films

During the past several years we have been developing technology for the creation of 3D microelectronics. Our 3D circuits are fabricated using standard bulk CMOS processing and are then transferred from one wafer to another. The transfer process allows alignment of the layers. The resulting structure consists of lower substrate and associated circuitry, with one or more thin-film circuit layers stacked on top, separated by bonding layers. We have developed an interconnection technology that allows layers to be electrically connected to one another. These interconnections are small and can be placed anywhere on the die. This unrestricted placement of interconnections gives our technology a unique advantage over other existing 3D interconnect techniques. We report our approach in this article     

A simple electrical method to determine the Si and oxidethicknesses in SOI materials

It is shown that the thickness of the silicon and oxide layers of a silicon-on-insulator (SOI) structure can be determined from high-frequency capacitance-voltage measurements. The test device consists of a Schottky diode in series with a Si-oxide-Si capacitor. The Si film and the substrate are n-type. The operation of this device is explained for n-type Si with the help of the energy-band diagrams. It is demonstrated that this simple test device can be implemented as a process monitor for silicon thickness control     

Integrated self-biased hexaferrite microstrip circulators formillimeter-wavelength applications

Planar microstrip Y-junction circulators have been fabricated from metallized 130-μm-thick self-biased strontium hexaferrite ceramic die, and then bonded onto silicon die to yield integrated circulator circuits. The impedance matching networks needed to transform the low-impedance circulator outputs were deployed on low-loss alumina or glass dielectrics to minimize circuit losses. These magnetically self-biased circulators show a normalized isolation and insertion loss of 33 and 2.8 dB, respectively, and a 1% bandwidth for an isolation of 20 dB. Application of small (H<1.5 kOe) magnetic bias fields improved the isolation and insertion loss values to 50 and 1.6 dB, respectively. This design may form the basis for future monolithic millimeter-wave integrated circulator circuits that do not require magnets     

Influence of nonuniform magnetic field on a ferrite junctioncirculator

We have analytically formulated the problem that a ferrite circulator junction is biased by a nonuniform magnetic field. Interport impedances of the junction can, therefore, be solved numerically. Nonuniform-bias field will reduce the transmission bandwidth, and the circulation condition is apt to be altered if the bias field shows nonuniformity near the center of the junction. Our calculation compares very well with measurements     

Strain analysis of silicon-on-insulator films produced by zonemelting recrystallization

Silicon-on-Insulator (SOI) wafers produced by the Zone-Melting-Recrystallization (ZMR) method were evaluated to determine the level of built-in strain. Micromechanical strain measurement structures were produced by surface micromachining the thin film silicon epitaxial layer. A variety of test structures and a new tensile strain measurement device were used to determine the level of strain in the material. Results indicated that the maximum strain in the ZMR material is less than 2×10^-4 and that there is a significant orientation dependence     

Rothko: a three-dimensional FPGA

Using transferred circuits and metal interconnections placed between layers of active devices anywhere on the chip, Rothko aims at solving utilization, routing, and delay problems of existing FPGA architectures. Experimental implementations have demonstrated important performance advantages