Design of systolic BN circuits in Galois fields based on quaternary logic

The BNoperation is known as an efficient basic operation in Galois fields GF(2k),and various algorithms and implementations using binary logic signals have already been proposed.In order to reduce the circuit complexity and long latency of BNoperations,a novel algorithm and its systolic architecture are proposed based on multiple-value logic(MVL).In the very large scale integration(VLSI)realization,a kind of multiple-valued current-mode(MVCM)circuit structure is presented and in which the combination of dynamic source-coupled logic(SCL)and different-pair circuits(DPCs)is employed to improve the switching speed and reduce the power dissipation.The performance is evaluated by HSPICE simulation with 0.18μm CMOS technology.The transistor numbers and the delay are superior to corresponding binary CMOS implementation.The combination of MVCM circuits and relevant algorithms based on MVL seems to be potential solution for high performance arithmetic operationsin Galois fields GF(2k).     

一种用于北斗导航接收机的全集成差分LNA

基于SMIC 180 nm CMOS工艺,设计了一款用于北斗导航接收机射频前端的低噪声放大器。在该低噪声放大器中,所有电感均为片上实现,提高了集成度;采用差分结构,提升了共模噪声抑制能力。LNA的输入和输出均为50 Ω标准阻抗匹配。测试结果表明,当频率为1.27 GHz时,该LNA的功率增益为15 dB,噪声系数(NF)为2.3 dB,1dB压缩点(P1dB)为－6 dBm。差分电路单路功耗为25 mW,芯片面积为1.2 mm²。