The influence of chloride-ion concentration on the Pitting of steel in simulated concrete environment

The influence of chloride-ion concentration on the pitting behaviour of steel in saturated Ca(OH)₂ solution was studied using the D.C. polarization technique. Results seem to indicate a threshold chloride level for the on-set of severe pitting around 3000 ppm, the pitting potential E_p exhibits dramatic drop and large hysteresis loops develop. The results provide insight into the pitting performance of steel in concrete and highlight the poor repassivation of this metal/environment system.     

Optimization of abrasive water jet cutting of ductile materials

Full factorial design of experiments was developed in order to investigate the effects of jet pressure, abrasive mixing rate, cutting feed, and plate thickness upon three response variables, surface finish of cutting wear zone, percentage proportion of striation free area, and maximum width of cut. The set of sixteen experiments was performed on each of the following two ductile materials: AISI 4340 (high strength low alloy steel, hardened to 49HRc) and Aluminum 2219. Analysis of Variance (ANOVA) was performed on experimental data in order to determine the significance of effects of different parameters on the performance measures. It was found that cutting feed and thickness were highly influential parameters, while abrasive mixing rate is influential upon surface roughness only. Strong interaction was found between jet pressure and workpiece material. Multi-criteria numerical optimization was performed in order to simultaneously maximize/minimize different combinations of performance measures.     

Deposition thickness based high-throughput nano-imprint template

International Technology Roadmap for Semiconductors 2003 projected nano-imprint lithography has the potential of high throughput, sub-20 nm resolution, and low cost [S.Y. Chou, P.R. Krauss, P.J. Renstrom, Appl. Phys. Lett. 67 (1995) 3144; Science 272 (1996) 85, J.A. Rogers, C. Mirkin, Mater. Res. Bull. 26 (2001)]. For nano-imprint lithography, a template with 1X resolution is required. The existing industrial infrastructure for supporting deep ultra violet 4X photo masks by e-beam and/or a laser beam scanning writer does not offer pitch (center-to-center distance of an array of patterned lines) less than ∼60 nm [<http://public.itrs.net/2003ITRS>]. For nano-imprint lithography to be accepted across the industry, a reproducible simple fabrication process to make a high resolution, single emboss template is essential [L. Jay Guo, J. Phys. D: Appl. Phys. 37 (2004) R123-R141]. Here we show, a general fabrication method and fabricated nano-imprint templates with sub-15 nm template line width and 10 nm pitch length through out the entire 200 mm wafer, varying the deposition thickness of multiple alternate films, using atomic layer deposition. Although multilayer nano-imprint templates and their exciting use have been demonstrated, [W.J. Dauksher et al., J. Vac. Sci. Technol. B 22 (2004) 3306, B. Heidari, et al., The 49th international conference on electron, ion and photon beam technology and nanofabrication, Orlando, Florida, 2005, William M. Tong, et al., Proc. SPIE 5751 (2005) 46-55, N.A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P.M. Petroff, J.R. Heath, Science 300 (2003) 112] such a small pitch was not shown and either complex lattice mismatch-based epitaxially grown films or unconventional etch chemistry was used. The bare necessity was a simple and economical fabrication process for a high throughput nano-imprint template. In that context, we have developed a template fabrication process using classical micro-fabrication techniques. Successful use of these techniques made the template fabrication process simple, economical, and expedient. Also a novel technique to provide flexible and accurate alignment for nanowire patterning has been described. In this technique, nanowire patterning is accomplished on the entire wafer with a single impression. Industry level batch-fabrication of our scheme illustrates its reproducibility and manufacturability. We anticipate, this simple, economical and time saving technique will help researchers and developers to perform their experiment on nano-scale feature patterned substrates easily and conveniently.     

Performance analysis of direct-detection optical CDMA communicationsystems with avalanche photodiodes

Direct-detection optical code-division multiple-access (CDMA) communication systems with avalanche photodiode (APD) photodetectors are investigated. A Chernoff upper bound, modified Chernoff upper bound, and Gaussian approximation on the probability of bit error are presented for general APDs and arbitrary {0,1}-valued optical signature sequences. Multiple-user interference, shot-noise, and receiver thermal noise effects on the bit error probability are studied in detail. One-coincidence optical orthogonal codes and prime codes are considered in the numerical analysis. Equal-weight orthogonal signaling formats that do not require dynamic estimation of the receiver threshold are proposed. The results suggest that equal-weight orthogonal signaling schemes are preferable to the on-off orthogonal signaling schemes commonly employed in the literature     

Design and Implementation of Optical Signal Reinstatement Technique for High DPSK RZ Transceiver Scheme

Wireless Personal Communications - Optical signal reinstatement (OSR) is a common technique used in high-speed communication systems. OSR can be achieved using various techniques such as;...     

Extracellular recordings from patterned neuronal networks using planar microelectrode arrays

Neuronal cell networks have been reconstructed on planar microelectrode arrays (MEAs) from dissociated hippocampal pyramidal neurons. Microcontact printing (microCP) and a photoresist-liftoff method were used to selectively localize poly-L-lysine (PLL) on the surface of MEAs. Haptotaxis led to the organization of the neurons into networks localized adjacent to microelectrodes. Various grids of PLL with 2-25-microm-wide lines spaced by 50-200 microm with 15-25-microm nodes at intersection points were used to guide cell body attachment and neurite outgrowth. Bursting activity with spike amplitude attenuation was observed, and multichannel recordings detected instances of coincident firing activity. Finally, we present here an extracellular recording from a approximately 2 microm bundle of guided neurites.     

Convergence behavior of the first-order time-delay digital tanlockloop

Convergence behavior of the previously proposed time-delay digital tanlock loop (TDTL) is analyzed. The approach is built on the actual number of steps required for the convergence of the phase error to its steady-state value. Unlike the first-order conventional digital tanlock loop (CDTL), the Lipschitz bound of TDTL is not a tight limit for the actual convergence time, especially for higher values of the absolute difference between the initial and the steady-state phase errors. For a frequency step input, the first-order TDTL locks faster than CDTL under suitable arrangement of the loop parameters     

Intelligibility improvements using binaural diverse sub-bandprocessing applied to speech corrupted with automobile noise

The paper reports on experiments assessing the capability of a diverse processing, multi-microphone sub-band adaptive signal processing scheme for improving the intelligibility of speech corrupted with automobile noise. Results from formal listening tests demonstrate a significant improvement in the intelligibility and quality of the processed speech. Spoken digits corrupted with automobile noise at a low and a high signal-to-noise ratio were used with two commercial speech recognisers. The results obtained with the recognisers did not demonstrate any statistically significant improvement due to processing in sub-bands     

A CMOS digitally programmable filter technique for VLSI applications

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current amplifiers (DCCAs) to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed analog/digital systems, the digital tuning feature of the proposed approach allows direct interfacing with the digital signal processing (DSP) part. Basic building blocks such as digitally programmable amplifiers, integrators, and simulated active inductors are given. Systematic designs of second-order filters are presented. Fully differential architectures of the proposed circuits are developed. Experimental results obtained from 0.5 μm standard CMOS chips are provided.     

Logic Design Validation via Simulation and Automatic Test Pattern Generation

We investigate an automated design validation scheme for gate-level combinational and sequential circuits that borrows methods from simulation and test generation for physical faults, and verifies a circuit with respect to a modeled set of design errors. The error models used in prior research are examined and reduced to five types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), wrong input errors (WIEs), and latch count errors (LCEs). Conditions are derived for a gate to be testable for GSEs, which lead to small, complete test sets for GSEs; near-minimal test sets are also derived for GCEs. We analyze undetectability in design errors and relate it to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. These experiments demonstrate that high coverage of the modeled errors can be achieved with small test sets obtained with standard test generation and simulation tools for physical faults.