超薄栅氧MOS器件传统关态栅泄漏电流研究

理论分析了MOSFET关态泄漏电流产生的物理机制,深入研究了栅氧化层厚度为1.4nm MOSFET传统关态下边缘直接隧穿栅泄漏现象.结果表明：边缘直接隧穿电流服从指数变化规律;传统关态下边缘直接隧穿对长沟道器件的影响大于短沟道器件;衬底反偏在一定程度上减小边缘直接隧穿泄漏电流.     

Improved low-distortion sigma-delta ADC with DWA for WLAN standards

An improved low distortion sigma-delta ADC(analog-to-digital converter) for wireless local area network standards is presented.A feed-forward MASH 2-2 multi-bit cascaded sigma-delta ADC is adopted;however,this work shows a much better performance than the ADCs which have been presented to date by adding a feedback factor in the second stage to improve the performance of the in-band SNDR(signal to noise and distortion ratio),using 4-bit ADCs in both stages to minimize the quantization noise.Data weighted ...     

Design of a high-order single-loop Σ△ ADC followed by a decimator in 0.18μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma–delta analog-to-digital converter followed by a multi-stage decimation filter.Design details and measurement results for the whole chip are presented for a TSMC 0.18μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz.The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz,the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB,a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz.The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm^2.     

基于0.18µm CMOS工艺的高阶单环∑△ADC以及降采样数字滤波器的设计

设计了一个过采样、高阶一位单环∑△模数转换器以及后级降采样数字滤波器。整个芯片采用TSMC 0.18µm CMOS工艺实现，芯片面积1mm×2mm，功耗为56mW。 调制器采用1.8V全差分电路结构，在过采样率64，时钟频率81.92MHz，640kHz带宽内，实测精度达到了15.32位，动态范围94dB。降采样数字滤波器的通带波纹小于0.01dB，阻带衰减75dB，过渡带为640kHz-740kHz。     

嵌入式SRAM的优化修复方法及应用

为了提高SRAM的成品率并降低其功耗,提出一种优化的SRAM.通过增加的冗余逻辑及电熔丝盒来代替SRAM中的错误单元,以提高其成品率;通过引入电源开启或关闭状态及隔离逻辑降低其功耗.利用二项分布计算最佳冗余逻辑,引入成品率边界因子判定冗余逻辑的经济性.将优化的SRAM64K×32应用到SoC中,并对SRAM64K×32 的测试方法进行了讨论.该SoC经90nm CMOS工艺成功流片, 芯片面积为5.6mm×5.6mm, 功耗为1997mW.测试结果表明:优化的SRAM64K×32 在每个晶圆上的成品率提高了9.267%,功耗降低了17.301%.     

Comparative analysis of different methods for image enhancement

Image enhancement technology plays a very important role to improve image quality in image processing. By enhancing some information and restraining other information selectively, it can improve image visual effect. The objective of this work is to implement the image enhancement to gray scale images using different techniques. After the fundamental methods of image enhancement processing are demonstrated, image enhancement algorithms based on space and frequency domains are systematically investigated and compared. The advantage and defect of the above-mentioned algorithms are analyzed. The algorithms of wavelet based image enhancement are also deduced and generalized. Wavelet transform modulus maxima（WTMM） is a method for detecting the fractal dimension of a signal, it is well used for image enhancement. The image techniques are compared by using the mean（μ）,standard deviation（？）, mean square error（MSE） and PSNR（peak signal to noise ratio）. A group of experimental results demonstrate that the image enhancement algorithm based on wavelet transform is effective for image de-noising and enhancement. Wavelet transform modulus maxima method is one of the best methods for image enhancement.     

多径传播环境下的无源UHF RFID系统电波传播模型

针对自由空间模型在预测射频识别系统识别距离时存在的偏差,综合考虑射频识别系统应用的多径传播环境,建立一种无源超高频射频识别系统电波传播模型,并重点分析了前向链路路径损耗的主要影响因素及其计算方法。基于该电波传播模型,探索性地提出实际环境下的无源超高频射频识别应用模拟思路。仿真和测量结果表明,该模型在预测无源超高频射频识别系统识别距离时更为准确。     

直接隧穿栅电流对CMOS逻辑电路的影响

对于纳米级的CMOS电路,由于MOS器件具有超薄的氧化层,栅隧穿漏电流的存在严重地影响了电路的正常工作。本文基于可靠性理论和电路级仿真深入地研究直接隧穿电流对CMOS逻辑电路的影响。仿真结果很好地与理论分析相符合,这些理论和仿真将有助于以后的集成电路设计。     

直接隧穿应力下超薄栅氧MOS器件退化

研究了栅氧厚度为1.4nm MOS器件在恒压直接隧穿应力下器件参数退化和应力感应漏电流退化. 实验结果表明,在不同直接隧穿应力过程中，应力感应漏电流（SILC）的退化和Vth的退化均存在线性关系. 为了解释直接隧穿应力下SILC的起因，建立了一个界面陷阱和氧化层陷阱正电荷共同辅助遂穿模型.