技术创造物联,应用驱动智慧——物联网经典技术与应用现场剖析

<正>以"技术创造物联,应用驱动智慧——物联网经典技术与应用现场剖析"为话题各专家代表展开了对话。主持人:中国电子学会物联网专家委员会副秘书长王新霞嘉宾:主题:依托物联网应用的智慧校园案例分析——南京邮电大学副校长朱洪波主题:"阿凡达"之手,智慧医疗应用现场演示——东南大学教授王志功主题:二维码在物联网及移动互联网中的应用实例分析——北京灵动快拍总经理王鹏飞     

自适应门限比较器设计

在电子设计和应用中,CMOS电平的电子系统接口往往需要同时兼容TTL电平.这往往需要在片外接电平转换芯片,从而增加了成本和面积.同时,外接的电平转换芯片也仅仅是解决了电平转换的问题,但并没有解决由于电平门限不同而导致的脉宽失真问题,尤其在低速情况下,该问题尤为严重.本文提出了一种自适应门限比较器单元电路,不仅可以兼容T...     

0.15μmInGaAs PHEMT50MHz-1GHz高线性CATV放大器设计

本文对应用于CATV（有线电视）的50MHz - 1GHz频段的低噪声和高线性度单片微波集成电路（MMIC）放大器进行了设计。设计采用并联电压交流负反馈和源极电流负反馈相结合以扩大带宽和高线性度。本文引入一种新的共源共栅管基极偏置以稳定工作点来进一步提高线性度。该电路由台湾稳懋半导体公司的0.15μm InGaAs PHEMT工艺制作。测试在有线电视频段50MHz-1GHz范围内和75欧姆测试匹配系统中进行。.测试结果表明芯片小信号增益为16.5dB,带内波动小于 1dB。噪声指数在带内为1.7-2.9dB。IIP3高达16dBm。CSO和CTB分别为68dBc和77dBc。芯片面积为0.56 mm2,而功耗在5V供电下为110mA。测试结果表明芯片展现了出色的噪声性能和高线性度,非常适合于有线电视系统。     

65-nm CMOS上带图案悬浮屏蔽的片上巴伦的特性

本文首先用一种简单的巴伦综合方法在工作频率范围内对巴伦结构进行估计,并借助电磁场仿真优化来检验估计的准确性,然后把优化后的巴伦（包括带屏蔽和不带屏蔽的两种情况）用于65-nm 1P6M CMOS工艺进行实现。测试结果显示图案悬浮屏蔽结构在频率范围内明显改善了插入损耗,并十分清晰地显示了线性改善的趋势。我们同样注意到图案悬浮屏蔽结构随着频率的增加逐渐改善了巴伦的相位平衡性,但对巴伦的幅度平衡性影响很小。为了得到器件本身的功率传输能力,我们提出一种方法从测得的三端口S参数直接获得巴伦的最大可用增益（Gmax）,并发现使用插入损耗比较的方式来检验屏蔽效果不是十分客观。另外阻性耦合效率也被用来衡量屏蔽效果。虽然图案悬浮屏蔽结构在测试中是完全对称的,但我们发现它对巴伦显示出不平衡的屏蔽效果。我们可以证明这种不平衡的屏蔽现象来自于巴伦本身的版图不平衡性。     

A wideband low power low phase noise dual-modulus prescaler

This paper describes a novel divide-by-32/33 dual-modulus prescaler(DMP).Here,a new combination of DFF has been introduced in the DMP.By means of the cooperation and coordination among three types,DFF, SCL,TPSC,and CMOS static flip-flop,the DMP demonstrates high speed,wideband,and low power consumption with low phase noise.The chip has been fabricated in a 0.18-μm CMOS process of SMIC.The measured results show that the DMP’s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier.The core area of the die without PAD is 57×30μm~2.Due to its excellent performance,the DMP could be applied to a PLL-based frequency synthesizer for many RF systems,especially for multi-standard radio applications.     

Characterization of on-chip balun with patterned floating shield in 65 nm CMOS

A simple method of balun synthesis is proposed to estimate the balun structure in the operating frequency band.Then,a careful optimization is implemented to evaluate the estimated structure by a series of EM simulations. In order to investigate the impact of the patterned floating shield(PFS),the optimized baluns with and without PFS are fabricated in a 65 nm 1P6M CMOS process.The measurement results demonstrate that the PFS obviously improves the insertion loss(IL) in the frequency range and a linear improving trend appears smoothly.It is also found that the PFS gradually improves the phase balance as the frequency increases,while it has a very slight influence on the magnitude balance.To characterize the device’s intrinsic power transfer ability,we propose a method to obtain the baluns’ maximum available gain directly from the measured 3-port S-parameters and find that IL-comparison may not be very objective when evaluating the shielding effect.We also use the resistive coupling efficiency to characterize the shielding effect,and an imbalanced shielding efficiency is found though the PFS is perfectly symmetric in the measurement.It can be demonstrated that this phenomenon comes from the intrinsic imbalance of our balun layout.     

A 3.16–7 GHz transformer-based dual-band CMOS VCO

A dual-band, wide tuning range voltage-controlled oscillator that uses transformer-based fourth-order(LC) resonator with a compact common-centric layout is presented. Compared with the traditional wide band(VCO), it can double frequency tuning range without degrading phase noise performance. The relationship between the coupling coefficient of the transformer, selection of frequency bands, and the quality factor at each band is investigated. The transformer used in the resonator is a circular asymmetric concentric topology. Compared with conventional octagon spirals, the proposed circular asymmetric concentric transformer results in a higher qualityfactor, and hence a lower oscillator phase noise. The VCO is designed and fabricated in a 0.18- m CMOS technology and has 75% wide tuning range of 3.16–7.01 GHz. Depending on the oscillation frequency, the VCO current consumption is adjusted from 4.9 to 6.3 m A. The measured phase noises at 1 MHz offset from carrier frequencies of 3.1, 4.5, 5.1, and 6.6 GHz are –122.5, –113.3, –110.1, and –116.8 d Bc/Hz, respectively. The chip area, including the pads, is 1.20.62 mm2 and the supply voltage is 1.8 V.     

基于移位多项式基优化并行RS伴随式计算电路的方法

研究了RS译码器的并行伴随式计算电路的结构优化,分别推导了并行度能整除和不能整除码长时的并行伴随式计算的表达式,并设计了相应的电路。针对并行实现会增加电路复杂度的问题,通过适当的变换,采用移位多项式基的方法,设计了低复杂度的并行伴随式计算改进电路。改进结构不仅降低了电路中有限域加法器的复杂度,并且通过将原有的多个小规模有限域乘法器简化为一个较大规模的乘法器,使得乘法器的复杂度也在很大程度上得到了降低。对并行度为8的RS(2040,2024)和RS(255,239)译码器的实验研究表明,上述的结构实现方法可比迭代匹配算法(IMA)节省约30%的资源,当并行度为64时,资源节省可达到50%。     

2.5Gb/s光纤通信用0.35μm CMOS芯片设计成功

随着计算机的迅速普及, 互联网的大规模建设, 多媒体通信和因特网的爆炸性扩展, 数据通信技术的开发和信息高速公路的建设变的日益迫切,而信息高速公路建设的关键在于光纤通信技术的开发和应用.     

电压激励神经信号重建微电子系统

采用0.6 μm CMOS工艺设计并仿真了电压激励的神经信号重建微电子系统.系统适用于卡肤电极(cuff electrode),由检测电路和功能电激励(FES)路组成.检测电路采集受损神经上端信号,以控制功能电激励电路,产生FES信号来激励受损神经下端.电路工作于±2.5 V.系统增益40～80 dB可调,3 dB带宽大于10 kHz,功耗8.2 mW.芯片尺寸为1.42 mm×1.34 mm.