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应用于高速CMOS图像传感器的10比特列并行循环式ADC   总被引:1,自引:1,他引:0  
韩烨  李全良  石匆  吴南健 《半导体学报》2013,34(8):085016-6
This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm~2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.  相似文献   
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张利地  肖立伊  石匆 《微处理机》2009,30(5):31-34,38
在当前的CMOS集成电路设计中,利用功率门控技术来降低静态功耗已经成为一种趋势.功率门控技术中,对电路进行分簇的算法和用来生成门控信号的控制电路是主要的设计部分.采用基于门的最大电流进行分簇的BOIG(Based on IMAX of Gate)算法和基于时间的功率门控控制电路,对ISCAS85系列的C432电路和ISCAS89系列的S1238电路进行了功率门控,并在性能、功耗和面积等方面进行了分析.结果表明,在满足性能的要求下,功耗降低了80%以上,面积有所增加.  相似文献   
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陈哲  底杉  石匆  刘力源  吴南健 《半导体学报》2014,35(10):105007-6
本文提出了一种兼容测距成像的图像传感器控制器,其测距原理基于采用连续波调制的飞行时间测距技术。控制器用于产生256×256高速CMOS图像传感器所需的可配置控制信号。图像传感器具有普通成像和测距成像两种工作模式,在两种工作模式下,通过配置参数产生的控制时序可以实现行滚动曝光与数字域的相关双采样。在逻辑电路级采用优化的设计方法,使得芯片面积和功耗得到优化。图像传感器控制器采用0.18 μm CMOS标准工艺制造,芯片面积为700×3380 μm2。在1.8 V供电电压和100 MHz工作频率下,由综合工具估算出的动态功耗为65 mW。测试结果验证了图像传感器控制器产生控制时序的功能。  相似文献   
4.
石匆  陈哲  杨杰  吴南健  王志华 《半导体学报》2014,35(9):095002-7
This paper presents a novel compact memory in the processing element (PE) for single-instruction multiple-data (SIMD) vision chips. The PE memory is constructed with 8×8 register cells, where one latch in the slave stage is shared by eight latches in the master stage. The memory supports simultaneous read and write on the same address in one clock cycle. Its compact area of 14.33 μm^2/bit promises a higher integration level of the processor. A prototype chip with a 64×64 PE array is fabricated in a UMC 0.18 μm CMOS technology. Five types of the PE memory cell structure are designed and compared. The testing results demonstrate that the proposed PE memory architecture well satisfies the requirement of the vision chip in high-speed real-time vision applications, such as 1000 fps edge extraction.  相似文献   
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