采用前端RC匹配技术的12位40兆赫兹无采样保持的流水线模数转换器

12位40兆赫兹流水线模数转换器采用了前端RC时间常数匹配技术和一组相应的不同占空比时钟时序方法。在不需要繁琐的后端版图仿真验证的情况下,可以很好的提高无采样保持结构流水线模数转换器的线性度。本设计采用0.13微米中芯国际工艺流片实现。通过取消采样保持器技术,运放共享技术和低功耗运放设计来确保低功耗和小面积的设计要求。在40兆赫兹采样时钟和10.2兆赫兹正弦输入信号下,此模数转换器可以达到78.2dB 的无杂散动态范围（SFDR）,60.5dB 的信噪失真比（SNDR）和 -75.5dB 的总谐波失真,在1.2伏的电源电压下,功耗仅为15.6毫瓦。     

A 12-bit 40-MS/s SHA-less pipelined ADC using a front-end RC matching technique

A 12-Bit 40-MS/s pipelined analog-to-digital converter(ADC) incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation.Employing SHA-less,opampsharing and low-power opamps for low dissipation and low cost,designed in 0.13-μm CMOS technology,the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range,60.5-dB of signal-to-noise-and -distortion ratio,and -75.5-dB of total harmonic distortion(the first 5 harmonics included) while consuming 15.6-mW from a 1.2-V supply.