超低比导通电阻SOI双栅槽型MOSFET

本文提出了超低比导通电阻(Ron,sp) SOI双栅槽型MOSFET(DG Trench MOSFET)。此MOSFET的特点是拥有双栅和一个氧化物槽：氧化物槽位于漂移区,一个槽栅嵌入氧化物槽,另一个槽栅延伸到埋氧层。首先,双栅依靠形成双导电沟道来减小Ron,sp;其次,氧化物槽不仅折叠漂移区,而且调制电场,从而减小元胞尺寸,增大击穿电压。当DG Trench MOSFET的半个元胞尺寸为3μm时,它的击穿电压为93V,Ron,sp为51.8mΩ?mm2。与SOI单栅MOSFET(SG MOSFET)和SOI单栅槽型MOSFET(SG Trench MOSFET)相比,在相同的BV下,DG Trench MOSFET的Ron,sp分别地降低了63.3%和33.8%。     

A Low On-Resistance SOI LDMOS using a Trench Gate and a Recessed Drain Ge Rui(葛锐), Luo Xiaorong(罗小蓉)?, Jiang Yongheng(蒋永恒), Zhou Kun(周坤),

本文提出了一种超低比导通电阻(R_on,sp) SOI槽栅凹漏MOSFET(TGRD MOSFET)。正向导通时,槽栅和凹漏的结构增加了导电区域,缩短了电流流经的路径,从而降低了比导通电阻。并且此结构中采用了RESURF结构提高了漂移区浓度,进一步降低了比导通电阻。当TGRD MOSFET的半个元胞尺寸为6.5μm时,它的击穿电压为97V,R_on,sp为0.985mΩ.cm₂。与SOI槽栅MOSFET(TG MOSFET)和常规MOSFET(Conventional MOSFET)相比,在相同的BV下,TGRD MOSFET的R_on,sp分别地降低了46%和83%。或者在相同的R_on,sp下,与SOI槽栅槽漏MOSFET(TGTD MOSFET)相比, BV提高了37%。     

Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

An ultra-low specific on-resistance(R_on,sp) silicon-on-insulator（SOI） double-gate trench-type MOSFET （DG trench MOSFET） is proposed.The MOSFET features double gates and an oxide trench:the oxide trench is in the drift region,one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide.Firstly,the double gates reduce R_on,sp by forming dual conduction channels.Secondly,the oxide trench not only folds the drift region,but also modulates the electric field,thereby reducing device pitch and increasing the breakdown voltage（BV）.A BV of 93 V and a R_on,sp of 51.8 mΩ·mm² is obtained for a DG trench MOSFET with a 3μm half-cell pitch.Compared with a single-gate SOI MOSFET（SG MOSFET） and a single-gate SOI MOSFET with an oxide trench（SG trench MOSFET）,the R_on,sp of the DG trench MOSFET decreases by 63.3%and 33.8% at the same BV,respectively.     

带有P型埋层的新型双栅SOI MOSFET

本文提出一种超低比导通电阻(Ron,sp)可集成的SOI 双栅triple RESURF (reduced surface field)的n型MOSFET (DG T-RESURF)。这种MOSFET具有两个特点：平面栅和拓展槽栅构成的集成双栅结构(DG),以及位于n型漂移区中的P型埋层。首先, DG形成双导电通道并且缩短正向导电路径,降低了比导通电阻。DG结构在反向耐压时起到了纵向场板作用,提高了器件的击穿电压特性。其次, P型埋层形成triple RESURF结构 (T-RESURF),这不仅增加了漂移区的浓度,而且调节了器件的电场。这在降低了比导通电阻的同时提高了击穿电压。最后,与p-body区连接在一起的P埋层和拓展槽栅结构,可以显著降低击穿电压对P型埋层位置的敏感性。通过仿真,DG T-RESURF的击穿电压为325V,比导通电阻为8.6 mΩ?cm2,与平面栅single RESURF MOSFET(PG S-RESURF)相比,DG T-RESURF的比导通电阻下降了63.4%,击穿电压上升9.8%。     

具有L型低阻导电通道的介质场增强SOI LDMOS

A low specific on-resistance（R on;sp/ SOI NBL TLDMOS（silicon-on-insulator trench LDMOS with an N buried layer） is proposed. It has three features： a thin N buried layer（NBL） on the interface of the SOI layer/buried oxide（BOX） layer, an oxide trench in the drift region, and a trench gate extended to the BOX layer.First, on the on-state, the electron accumulation layer forms beside the extended trench gate; the accumulation layer and the highly doping NBL constitute an L-shaped low-resistance conduction path, which sharply decreases the R on;sp. Second, in the y-direction, the BOX＇s electric field（E-field） strength is increased to 154 V/ m from48 V/ m of the SOI Trench Gate LDMOS（SOI TG LDMOS） owing to the high doping NBL. Third, the oxide trench increases the lateral E-field strength due to the lower permittivity of oxide than that of Si and strengthens the multiple-directional depletion effect. Fourth, the oxide trench folds the drift region along the y-direction and thus reduces the cell pitch. Therefore, the SOI NBL TLDMOS structure not only increases the breakdown voltage（BV）, but also reduces the cell pitch and R on;sp. Compared with the TG LDMOS, the NBL TLDMOS improves the BV by 105% at the same cell pitch of 6 m, and decreases the R on;sp by 80% at the same BV.     

High voltage SOI LDMOS with a compound buried layer

An SOI LDMOS with a compound buried layer (CBL) was proposed. The CBL consists of an upper buried oxide layer (UBOX) with a Si window and two oxide steps, a polysilicon layer and a lower buried oxide layer (LBOX). In the blocking state, the electric field strengths in the UBOX and LBOX are increased from 88 V/μm of the buried oxide (BOX) in a conventional SOI (C-SOI) LDMOS to 163 V/μm and 460 V/μm by the holes located on the top interfaces of the UBOX and LBOX, respectively. Compared with the C-SOI LDMOS, the CBL LDMOS increases the breakdown voltage from 477 to 847 V, and lowers the maximal temperature by 6 K.