超低比导通电阻SOI双栅槽型MOSFET

本文提出了超低比导通电阻(Ron,sp) SOI双栅槽型MOSFET(DG Trench MOSFET)。此MOSFET的特点是拥有双栅和一个氧化物槽：氧化物槽位于漂移区,一个槽栅嵌入氧化物槽,另一个槽栅延伸到埋氧层。首先,双栅依靠形成双导电沟道来减小Ron,sp;其次,氧化物槽不仅折叠漂移区,而且调制电场,从而减小元胞尺寸,增大击穿电压。当DG Trench MOSFET的半个元胞尺寸为3μm时,它的击穿电压为93V,Ron,sp为51.8mΩ?mm2。与SOI单栅MOSFET(SG MOSFET)和SOI单栅槽型MOSFET(SG Trench MOSFET)相比,在相同的BV下,DG Trench MOSFET的Ron,sp分别地降低了63.3%和33.8%。     

A new integrated SOI power device based on self-isolation technology

A new SOI LDMOS structure with buried n-islands(BNIs) on the top interface of the buried oxide(BOX) is presented in a p-SOI high voltage integrated circuits(p-SOI HVICs),which exhibits good self-isolation performance between the power device and low-voltage control circuits.Furthermore,both the donor ions of BNIs and holes collected between depleted n-islands not only enhance the electric field in BOX from 32 to 113 V/μm,but also modulate the lateral electric field distribution,resulting in an improvemen...     

Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

An ultra-low specific on-resistance(R_on,sp) silicon-on-insulator（SOI） double-gate trench-type MOSFET （DG trench MOSFET） is proposed.The MOSFET features double gates and an oxide trench:the oxide trench is in the drift region,one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide.Firstly,the double gates reduce R_on,sp by forming dual conduction channels.Secondly,the oxide trench not only folds the drift region,but also modulates the electric field,thereby reducing device pitch and increasing the breakdown voltage（BV）.A BV of 93 V and a R_on,sp of 51.8 mΩ·mm² is obtained for a DG trench MOSFET with a 3μm half-cell pitch.Compared with a single-gate SOI MOSFET（SG MOSFET） and a single-gate SOI MOSFET with an oxide trench（SG trench MOSFET）,the R_on,sp of the DG trench MOSFET decreases by 63.3%and 33.8% at the same BV,respectively.     

基于自隔离技术的可集成SOI高压功率器件新结构

SOI功率器件的高耐压和高、低压间良好的隔离效果是SOI高压功率集成电路（SOI HVIC）的两项关键技术。本文提出在埋氧层（buried oxide layer,BOX）上表面处埋N岛 (buried n-islands,BNI) 的SOI LDMOS高压功率器件新结构,该结构采用自隔离技术使SOI HPIC中高压功率器件与低压控制电路单元之间达到理想的隔离效果。此外,N岛中的施主离子和位于耗尽N岛间的空穴使BOX层的电场强度从32V/μm增加到113V/μm,同时对漂移区表面电场分布进行调制,最终使器件击穿电压（BV）显著提高。实验测得一个BNI SOI LDMOS样品的耐压为673V,并在SOI HVPIC中表现出良好的隔离特性。