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In this paper we present a new, adaptive spatial-derivative circuit for CMOS image sensors. The circuit removes its offset as a natural part of its operation using a combination of electron tunneling and hot-electron injection to add or remove charge on a floating-gate of an auto-zeroing amplifier. We designed, fabricated and successfully tested a chip with the circuit. Test results show that the circuit reduces the offsets by more than an order of magnitude.  相似文献
2.
We have developed a complementary pair of pFETand nFET floating-gate silicon MOS transistors foranalog learning applications. The memory storage is nonvolatile;hot-electron injection and electron tunneling permit bidirectionalmemory updates. Because these updates depend on both the storedmemory value and the transistor terminal voltages, the synapsescan implement a learning function. We have derived a memory-updaterule for both devices, and have shown that the synapse learningfollows a simple power law. Unlike conventional EEPROMs, thesynapses allow simultaneous memory reading and writing. Synapsetransistor arrays can therefore compute both the array output,and local memory updates, in parallel. We have fabricated prototypesynaptic arrays; because the tunneling and injection processesare exponential in the transistor terminal voltages, the writeand erase isolation between array synapses is better than 0.01 percentThe synapses are small, and typically are operated at subthresholdcurrent levels; they will permit the development of dense, low-powersilicon learning systems.  相似文献
3.
We describe a family of current-mode circuits with multiple inputs and multiple outputs whose output currents are products and/or quotients of powers of the input currents. These circuits are made up of multipleinput floating-gate MOS (FGMOS) transistors operating in the subthreshold regime. The powers are set by capacitor ratios; hence, they can be quite accurate. We analyze the general family of such circuits and present experimental data from several members that we fabricated in a standard 2m double-poly p-well process through MOSIS.  相似文献
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