A carry-free 54b×54b multiplier using equivalent bitconversion algorithm

An equivalent bit conversion algorithm (EBCA) is proposed to eliminate the need for final carry propagation in the redundant binary (RB) to normal binary (NB) conversion step for RB multiplication. The multiplication process helps with the carry-free conversion step by eliminating certain combinations of RB product. When the EBCA is applied, conventional power-consuming carry-propagating adders are replaced by simple, minimum-sized carry-free converters, and the entire multiplication process can be made free of carry propagation from input to output. The method employed in this work reduces 40% of the total power and 30% of the total multiplication time in the final adder stage of traditional multipliers. The prototype fabricated in 0.35-μm CMOS demonstrates that the 54 b×54 b multiplier consumes only 53.4 mW at 3.3 V for 74-MHz operation     

Associative processors and memories: a survey

The functional structure of a classical content-addressable memory (CAM) and its realization at the transistor level are described. Some unorthodox CAM approaches are briefly examined. Associative processor systems are discussed, and application-specific CAM architectures to support artificial intelligence features are surveyed. Limitations of associative processing and ways to circumvent them are addressed. The use of parallel cellular logic is considered     

Comments on "A carry-free 54 b/spl times/54 b multiplier using equivalent bit conversion algorithm"

For original paper see ibid., vol. 36, no. 10, p. 1538-1545 (Oct. 2001). In the aforementioned paper by Kim et al., a multiplier is presented which produces the result in radix-2 signed-digit representation. It is claimed that this representation can be converted into conventional magnitude representation by an algorithm which has no carry propagation. To the commenters this algorithm seems incorrect. The critical situation is a string which consists of a sequence of zeros followed by a -1; in such a case a carry is needed and the algorithm proposed is deemed incorrect. Consequently, it is pointed out that the proposed algorithm produces a correct multiplication result in conventional magnitude representation only if the signed-digit string does not have a sequence of 0's followed by a -1. The commenters show a multiplication example using the proposed conversion algorithm in which this situation occurs.     

Fault tolerance in highly parallel hardware systems

As the demand for highly parallel systems grows, the vast amount of concurrently operating hardware involved can make it difficult to guarantee proper system behavior. Problems arise both from permanent and transient hardware faults and from errors caused by improper programming. A number of fault tolerance solutions have emerged. Following a survey of fault tolerance in arrays, a discussion of solutions for more specialized architectures is presented     

Fault tolerance

This special issue reports on the methodological progress in some selected areas of fault tolerance as well as practical experience gained by developing concrete fault-tolerant systems. Correspondingly, the issue contains contributions from the research community as well as from industry     

The associative processor system CAPRA: architecture andapplications

The basic features of a content-addressable processor/register array (CAPRA) are discussed. The features are the inclusion of logic elements directly within the word cells or bit cells of memory, use of a maskable decoder to enable multiaccess to the memory and computing devices of the array, activity flags within the cells of the array to enable flexible definition of activity patterns, and integration of sensor elements for the direct parallel input of optical data. The architecture's potential applications in database support, basic numerical tasks, and image processing are discussed