MOS 场引晶体管双极理论和实验

提出场引晶体管双极理论.替代已55年久,1952 Shockley发明单极理论.解释近来双栅纳米硅MOS晶体管实验特性--两条电子和两条空穴表面沟道,同时并存.理算晶体管输出特性和转移特性,包括实用硅基及栅氧化层厚度.理算比较最近报道实验,利用硅FinFET,含(金属/硅)和(p/n)结,源和漏接触.实验支持双极理论.建议采用单管,实现CMOS倒相电路和SRAM存储电路.     

双极场引晶体管:Ⅱ.飘移扩散理论(双MOS栅纯基)

本文描述双极场引晶体管(BiFET)飘移扩散理论,包括薄纯基上两个等同金属氧化物硅(MOS)栅.把两维晶体管分解成两个一维晶体管,以表面势为参变量,得到解析方程.提供实用硅基和氧化层厚度范围内,随直流电压变化,输出和转移电流和电导总量和飘移扩散分量.显著部分的飘移电流来自横向电场平方的纵向梯度.     

MOS Capacitance-Voltage Characteristics Ⅱ.Sensitivity of Electronic Trapping at Dopant Impurity from Parameter Variations

Low-frequency and high-frequency Capacitance-Voltage（C-V） curves of Metal-Oxide-Semiconductor Capacitors（MOSC）,including electron and hole trapping at the dopant donor and acceptor impurities,are presented to illustrate giant trapping capacitances,from>0.01C_ox to>10C_ox.Five device and materials parameters are varied for fundamental trapping parameter characterization,and electrical and optical signal processing applications.Parameters include spatially constant concentration of the dopant-donor-impurity electron trap,N_DD,the ground state electron trapping energy level depth measured from the conduction band edge, E_C—E_D,the degeneracy of the trapped electron at the ground state,g_D,the device temperature,T,and the gate oxide thickness,x_OX.     

The Bipolar Field-Effect Transistor:Ⅶ.The Unipolar Current Mode for Analog-RF Operation(Two-MOS-Gates on Pure-Base)

This paper reports the DC steady-state current-voltage and conductance-voltage characteristics of a Bipolar Field-Effect Transistor(BiFET) under the unipolar(electron) current mode of operation,with bipolar(elec-tron and hole) charge distributions considered.The model BiFET example presented has two MOS-gates on the two surfaces of a thin pure silicon base layer with electron and hole contacts on both edges of the thin base.The hole contacts on both edges of the thin pure base layer are grounded to give zer...     

The Bipolar Field-Effect Transistor: ⅩⅢ. Physical Realizations of the Transistor and Circuits (One-Two-MOS-Gates on Thin-Thick Pure-Impure Base)

This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These ex-amples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impure-thin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concen-tration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.     

双极场引晶体管:VI.CMOS电压倒相电路(双MOS栅纯基)

本文报告了硅互补金属氧化层硅（CMOS）电压倒相电路的直流稳态电压和电流转移特性和功率耗散. 这电路用一只实际的﹑纳米尺度的双极场引晶体管(BiFET)实现. 通过数字求解五个偏微分方程,可获得这些电学特性. 方程是基于这种器件结构：在薄纯硅基层的两表面上各有一个MOS栅,在这薄基的两端都有电子和空穴接触. 内部条件和CMOS边界条件用于三种势（静电势和电子及空穴电化学势）. 用一台装有Windows XP-PRO下的64位FORTRAN语言的双核个人计算机,快速地计算出一系列曲线.     

场引晶体管理论:XI.双极电化电流（薄及厚、纯及不纯基体,单及双MOS栅极）

场引晶体管本质双极,包括电子和空穴表面和体积沟道和电流,一或多个外加横向控制电场．自1952年Shockley发明,55年来它被认为单极场引晶体管,因电子电流理论用多余内部和边界条件,不可避免忽略空穴电流．多余条件,诸如电中性和常空穴电化电势,导致仅用电子电流算内部和终端电学特性的错误解．当忽略的空穴电流与电子电流可比,可在亚阈值区和强反型区,错误解有巨大误差．本文描述普适理论,含有电子和空穴沟道和电流．用z轴宽度方向均匀的直角平行六面体（x,y,z）晶体管,薄或厚、纯或杂基体,一或二块MOS栅极,描述两维效应及电势、电子空穴电化电势的正确内部和边界条件．没用多余条件,导出四种常用MOS晶体管,直流电流电压特性完备解析方程：半无限厚不纯基上一块栅极（传统的Bulk MOSFET）,与体硅以氧化物绝缘的不纯硅薄层上一块栅极（SOI）,在沉积到绝缘玻璃的不纯硅薄层上一块栅极（SOI TFT）,和薄纯基上两块栅极（FinFETs）．     

场引晶体管双极理论:Ⅹ.基本物理和理论(所有器件结构)

本文描述半导体场引晶体管器件物理和理论所用的根本原则,它适用电场中有两种载流子的器件.讨论边界条件对器件电流电压特性的重要性.作为例子,计算两种边界条件下的转移直流电压特性:电势边界给出很高、流进内禀晶体管、飘移限制抛物型电流,电化学势边界仿真电子和空穴接触,给出很低、越过势垒注入、扩散限制电流,具有理想、每量级60mV、指数型亚阈值区倾斜.双MOS栅薄纯基硅场引晶体管为典型结构.     

MOS场引晶体管双极理论和实验

提出场引晶体管双极理论.替代已55年久,1952 Shockley发明单极理论.解释近来双栅纳米硅MOS晶体管实验特性--两条电子和两条空穴表面沟道,同时并存.理算晶体管输出特性和转移特性,包括实用硅基及栅氧化层厚度.理算比较最近报道实验,利用硅FinFET,含(金属/硅)和(p/n)结,源和漏接触.实验支持双极理论.建议采用单管,实现CMOS倒相电路和SRAM存储电路.     

MOS Capacitance–Voltage Characteristics: IV. Trapping Capacitance from 3-Charge-State Impurities

Metal-Oxide-Semiconductor Capacitance-Voltage (MOSCV) characteristics containing giant carrier trapping capacitances from 3-charge-state or 2-energy-level impurities are presented for not-doped, n-doped, p-doped and compensated silicon containing the double-donor sulfur and iron, the double-acceptor zinc, and the amphoteric or one-donor and one-acceptor gold and silver impurities. These impurities provide giant trapping capacitances at trapping energies from 200 to 800 meV (50 to 200 THz and 6 to 1.5 μm), which suggest potential sub-millimeter, far-infrared and spin electronics applications.