Exploring the security landscape: NoC-based MPSoC to Cloud-of-Chips

In this paper, we present a detailed and systematic overview of communication security aspects of Multi-Processor Systems-on-Chip (MPSoC) and the emerging potential threats on the novel Cloud-of-Chips (CoC) paradigm. The CoC concept refers to highly scalable and composable systems, assembled not only at system design-time using RTL, like traditional SoC, but also at integrated circuit (IC) packaging time thanks to 3D-IC integration technology. Practical implementation of CoC systems needs to solve the problem of scalable, configurable and secure communication not only between different functional blocks in a single ICs, but also between different ICs in a single package, and between different packages on the same or different PCBs and even between different systems. To boost such extremely flexible communication infrastructure CoC system relies on Software-Defined Network-on-Chip (SDNoC) paradigm that combines design-time configurability of on-chip systems (NoC) and highly configurable communication of macroscopic systems (SDN). This study first explores security threats and existing solutions for traditional MPSoC platforms. Afterwards, we propose SDNoC as an alternative to MPSoC communication security, and we further extend our discussion to CoC systems to identify additional security concerns. Moreover, we present a comparison of SDNoC based approach over existing approaches and discuss its potential advantages.     

Protection switching schemes and mapping strategies for fail-operational hard real-time NoCs

Communication infrastructures designed for mixed-critical MPSoCs must provide isolation of traffic, hard real-time guarantees, and fault-tolerance. In previous work, we proposed the combination of protection-switching with a hybrid Time-Division-Multiplexed (TDM) and packet-switched Network-on-Chip (NoC) to achieve all three goals. In this paper, we present an FPGA implementation of such a NoC with all its features. We give synthesis results for the hybrid NoC, including the network interface, and show that our router uses over 32% fewer LUTs and registers than a competitive state-of-the-art router for mixed-critical MPSoC. We then explore different channel and task mapping strategies for critical applications which use protection switching and evaluate the effect these mappings have on the best-effort (BE) traffic in the system. Results show, that spreading out the critical traffic rather than naively dividing the system in critical and non-critical application domains is advantageous or even necessary in many cases and can allow for up to 13% more BE traffic. We give a comprehensive trade-off analysis of three protection switching schemes—1:n, 1:1, and 1+1—and show that 1+1 protection has less than half the worst case latency for critical traffic that 1:n and 1:1 protection have. At the same time, 1+1 protection, on average, only causes a 1.18% earlier saturation rate for BE traffic, which we consider to be affordable. We conclude that 1+1 protection is ideally suited for use in mixed-critical systems with high safety requirements.     

Service based communication for MPSoC platform-SegBus

MPSoC platforms offer solutions to deal with communication limitations for multiple cores on single chip, but many new issues arise within the context. The SegBus platform is one of the solutions for application deployment on multi-core applications. There are many applications where identical data is transferred from the same source towards different destinations. Multicast services may come as a performance improving factor for the interconnection platform, together with interrupt service.In this paper, the task is to analyze, how different services can be designed for the SegBus platform and observe the improvement in system performance. The designer can select the services according to the requirements. The running example is represented by the H.264 encoder. The SegBus platform architecture, the communication mechanism, the allocation of processing elements on the platform, the communication services and their implementation are the main topics elaborated here.     

Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling

State-of-the-art devices in the consumer electronics market are relying more and more on Multi-Processor Systems-On-Chip (MPSoCs) as an efficient solution to meet their multiple design constrains, such as low cost, low power consumption, high performance and short time-to-market. In fact, as technology scales down, logic density and power density increase, generating hot spots that seriously affect the MPSoC performance and can physically damage the final system behavior. Moreover, forthcoming three-dimensional (3D) MPSoCs can achieve higher system integration density, but the aforementioned thermal problems are seriously aggravated. Thus, new thermal exploration tools are needed to study the temperature variation effects inside 3D MPSoCs. In this paper, we present a novel approach for fast transient thermal modeling and analysis of 3D MPSoCs with active (liquid) cooling solutions, while capturing the hardware-software interaction. In order to preserve both accuracy and speed, we propose a close-loop framework that combines the use of Field Programmable Gate Arrays (FPGAs) to emulate the hardware components of 2D/3D MPSoC platforms with a highly optimized thermal simulator, which uses an RC-based linear thermal model to analyze the liquid flow. The proposed framework offers speed-ups of more than three orders of magnitude when compared to cycle-accurate 3D MPSoC thermal simulators. Thus, this approach enables MPSoC designers to validate different hardware- and software-based 3D thermal management policies in real-time, and while running real-life applications, including liquid cooling injection control.     

A Mapping Framework Based on Packing for Design Space Exploration of Heterogeneous MPSoCs

The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to satisfy this demand. But to be able to take advantage of these systems, new strategies are required to map applications to such a system and to evaluate the systems performance at a very early design stage. We will present a framework for static, analytical, bottom-up temporal and spatial mapping of applications to MPSoCs based on packing. This mapping framework allows easy performance evaluation and design space exploration of heterogeneous systems on chip.

Cognitive Radio Design on an MPSoC Reconfigurable Platform

Cognitive Radio has been proposed as a promising technology for solving today’s spectrum scarcity problem by means of dynamic spectrum access. The multiprocessor system-on-chip (MPSoC) reconfigurable platform is proposed as an enabling technology for cognitive radio. In this paper, we propose a design methodology based on task transaction level interface for the design of cognitive radio baseband on an MPSoC reconfigurable platform. The reconfiguration of a novel, low-complexity fast Fourier transform for orthogonal frequency-division multiplexing based Cognitive Radio is used as a design case to show the effectiveness of the methodology for modelling the dynamic behavior of Cognitive Radio and facilitating the platform implementation.

多核SoC可扩展性设计技术研究

近年来,使用多核SoC代替传统的单处理器系统,在提高系统并行性方面显示出了巨大的优势.本文在已有层次化总线结构MPSoC的基础上,研究多核SoC原型芯片可扩展性设计问题.在RTL级设计了上述平台,并用FPGA进行原型验证,以流水矩阵乘法为例研究其在不同工作负载下的加速比变化.实验结果表明,在6个处理器的情形下,循环次数为6次时加速比仅为4.10;随着循环次数增多,加速比可达5.48.研究表明多核层次化总线原型芯片的性能提升百分比以及面积增加百分比与处理器数目成正比.可以通过增加处理器的数目来提升MPSoC原型芯片的性能.     

Resource-awareness on heterogeneous MPSoCs for image processing

Multiprocessor system-on-chip (MPSoC) designs offer a lot of computational power assembled in a compact design. The computing power of MPSoCs can be further augmented by adding massively parallel processor arrays (MPPA) and specialized hardware with instruction-set extensions. On-chip MPPAs can be used to accelerate low-level image-processing algorithms with massive inherent parallelism. However, the presence of multiple processing elements (PEs) with different characteristics raises issues related to programming and application mapping, among others. The conventional approach used for programming heterogeneous MPSoCs results in a static mapping of various parts of the application to different PE types, based on the nature of the algorithm and the structure of the PEs. Yet, such a mapping scheme independent of the instantaneous load on the PEs may lead to under-utilization of some type of PEs while overloading others.In this work, we investigate the benefits of using a heterogeneous MPSoC for accelerating various stages within a real-world image-processing algorithm for object-recognition. A case study demonstrates that a resource-aware programming model called Invasive Computing helps to improve the throughput and worst observed latency of the application program, by dynamically mapping applications to different types of PEs available on a heterogeneous MPSoC.     

多核片上系统时钟网络结构模型与仿真分析

对多核片上系统(MPSoC)而言,随着集成度和性能的提升,时钟网络的结构愈发重要.研究了基于结构建模的多路全局/局域时钟网络的结构建模与分析.通过建立多级级联,分别从主干、支干和接入三层对时钟网络的结构进行建模.针对运算单元接入数、单行中肋排数目、运算单元中输入时钟数目以及时钟区域数等几方面,评估了时钟网络性能.以Stratix V E FPGA为例对时钟网络综合分析,分析结果表明,四象限的对称结构权衡了多项性能指标,是最优的时钟网络结构,可以作为一种通用结构应用在目前主流MPSoC上.     

面向MPSoC多核AMP架构的运行方案研究

本文针对Zynq UltraScale+ MPSoC硬件平台,通过分析对比现有的非对称多处理架构方案,提出一种简洁的AMP运行方案,实现1个Cortex-A53核运行Linux系统,其他3个Cortex-A53核运行裸核系统功能.本文从分析多核启动机制入手,实现一种Linux用户态动态加载启动多核方案,设计多核监督模块...