基于软件校准的短波发射机功率控制系统设计

短波发射机功率稳定一直是通信领域致力改善的重点问题,短波发射机功率不稳定会直接影响无线电通信质量,造成通信失真、表达不清晰等问题。针对上述问题,基于软件校准设计短波发射机功率控制系统。该系统借鉴MVC设计模式搭建系统数据库层、业务逻辑层、控制层以及界面显示层基础框架；将功率计与短波发射机相连,实时采集工作状态下的短波发射机功率数据,通过信号处理器实施处理后并存储,借鉴传输元件,将数据发送到控制器,通过控制器校准短波发射机功率与预期之间的偏差,以偏差量为输入,利用改进PID运算得出控制量,生成控制命令,通过输入输出信号接口板输出命令,控制驱动装置调节短波发射机运行参数,实现功率控制。结果表明：与 控制系统、自动调谐系统应用相比较,在所设计系统应用控制下,100s内短波发射机的功率变化曲线与预期曲线之间的拟合优度指数更大,更接近1,优于对比系统,说明相比于对比系统。本系统控制表现更好,更能维持短波发射机功率稳定,达到了研究目标。     

2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S₂₁), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S₁₁ and S₂₂ are less than −10 dB. The input compression point (P_1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm².     

直角坐标在软件开发中的应用研究

为简化不同软件开发技术处理界面中组件关系的算法,增强使用数学模型解决软件开发中算法设计的能力,全面分析和总结直角坐标系在界面设计中的应用十分必要。通过对不同开发技术处理界面设计的分析,界面中组件位置关系实质上都可以转化为坐标关系的计算。本文列举了直角坐标系在Python编程、Android编程、Java编程和Unity编程中的应用,以期给相应的算法设计提供借鉴思路。     

Rethinking Enterprise Architecture for Sustainable Energy System Development

The development of a sustainable energy system throughout an enterprise is a complex task, which requires an agile holistic approach. Such an approach needs to include a variety of objectives including energy strategy formation and strategic decision-making, which are directly related to the analysis and management of the main areas of sustainable development:The economic, technological, environmental, and social. These multidimensional requirements of sustainability are often difficult to achieve within the enterprise, because these aspects are interrelated and influenced by various internal and external environment factors. This paper first reviews the main challenges for an energy system, and then demonstrates how a strategic agile enterprise architecture driven approach could effectively guide the sustainable energy system development. The study presented in this paper provides a holistic approach that contributes to the advancement and usage of literature dealing with issues of sustainable energy system development and agile enterprise architecture, which has not been discussed before to any great extent.     

Resistive switching characteristics of ZnO–graphene quantum dots and their use as an active component of an organic memory cell with one diode-one resistor architecture

We investigated the resistive switching characteristics of a polystyrene:ZnO–graphene quantum dots system and its potential application in a one diode-one resistor architecture of an organic memory cell. The log–log I–V plot and the temperature-variable I–V measurements revealed that the switching mechanism in a low-current state is closely related to thermally activated transport. The turn-on process was induced by a space-charge-limited current mechanism resulted from the ZnO–graphene quantum dots acting as charge trap sites, and charge transfer through filamentary path. The memory device with a diode presented a ∼10³ I_ON/I_OFF ratio, stable endurance cycles (10² cycles) and retention times (10⁴ s), and uniform cell-to-cell switching. The one diode-one resistor architecture can effectively reduce cross-talk issue and realize a cross bar array as large as ∼3 kbit in the readout margin estimation. Furthermore, a specific word was encoded using the standard ASCII character code.     

Combined hardware–software multi-parallel prefiltering on the Convey HC-1 for fast homology detection

Protein databases used in research are huge and still grow at a fast pace. Many comparisons need to be done when searching similar (homologous) sequences for a given query sequence in these databases. Comparing a query sequence against all sequences of a huge database using the well-known Smith–Waterman algorithm is very time-consuming. Hidden Markov Models pose an opportunity for reducing the number of entries of a database and also enable to find distantly homologous sequences. Fewer entries are achieved by clustering similar sequences in a Hidden Markov Model. Such an approach is used by the bioinformatics tool HHblits. To further reduce the runtime, HHblits uses two-level prefiltering to reduce the number of time-consuming Viterbi comparisons. Still, prefiltering is very time-consuming. Highly parallel architectures and huge bandwidth are required for processing and transferring the massive amounts of data. In this article, we present an approach exploiting the reconfigurable, hybrid computer architecture Convey HC-1 for migrating the most time-consuming part. The Convey HC-1 with four FPGAs and high memory bandwidth of up to 76.8 GB/s serves as the platform of choice. Other bioinformatics applications have already been successfully supported by the HC-1. Limited by FPGA size only, we present a design that calculates four first-level prefiltering scores per FPGA concurrently, i.e. 16 calculations in total. This score calculation for the query profile against database sequences is done by a modified Smith–Waterman scheme that is internally parallelized 128 times in contrast to the original Streaming ‘Single Instruction Multiple Data (SIMD)’ Extensions (SSE)-supported implementation where only 16-fold parallelism can be exploited and where memory bandwidth poses the limiting factor. Preloading the query profile, we are able to transform the memory-bound implementation to a compute- and resource-bound FPGA design. We tightly integrated the FPGA-based coprocessor into the hybrid computing system by employing task-parallelism for the two-level prefiltering. Despite much lower clock rates, the FPGAs outperform SSE-based execution for the calculation of the prefiltering scores by a factor of 7.9.     

Simplified anode architecture for PEMFC systems based on alternative fuel feeding: Experimental characterization and optimization for automotive applications

The need to reduce PEMFC systems cost as well as to increase their durability is crucial for their integration in various applications and especially for transport applications. A new simplified architecture of the anode circuit called Alternating Fuel Feeding (AFF) offers to reduce the development costs. Requiring a new stack concept, it combines the simplicity of Dead-End Anode (DEA) with the operation advantages of the hydrogen recirculation. The three architectures (DEA, recirculation and AFF) are compared in terms of performance on a 5-kW test bench in automotive conditions, through a sensitivity analysis. A gain of 17% on the system efficiency is observed when switching from DEA to AFF. Moreover, similar performances are obtained both for AFF and for recirculation after an accurate optimization of the AFF tuning parameters. Based on DoE data, a gain of 25% on the weight of the anodic line has been identified compared to pulsed ejector architecture and 43% with the classic recirculation architecture with blower only (Miraï).     

基于哈希链的软件定义网络路径安全

针对软件定义网络中，控制器无法保证下发的网络策略能够在转发设备上得到正确执行的安全问题，提出一种新的转发路径监控安全方案。首先以控制器的全局视图能力为基础，设计了基于OpenFlow协议的路径凭据交互处理机制；然后采用哈希链和消息验证码作为生成和处理转发路径凭据信息的关键技术；最后在此基础上，对Ryu控制器和Open vSwitch开源交换机进行深度优化，添加相应处理流程，建立轻量级的路径安全机制。测试结果表明，该机制能够有效保证数据转发路径安全，吞吐量消耗比SDN数据层可信转发方案（SDNsec）降低20%以上，更适用于路径复杂的网络环境，但时延和CPU使用率的浮动超过15%，有待进一步优化。     

AD HOC网络管理综述

由于AD HOC网络自身的特点，其网络管理很多方面与固定网络不同，如移动性管理和体系结构管理等。讨论了AD HOC网络管理的各个方面，并列举了各个方面的设计思路和已有的相关算法的简介。