一种考虑电压岛边界约束的多电压布图算法

多电压设计(multiple supply voltage,MSV)是降低SoC功耗的有效方法之一.为便于电压岛供电引脚的放置,提出了一种考虑电压岛边界约束的多电压布图算法.首先,基于切分树表示的布图解特点,提出一种边界检查算法快速确定所有模块的边界信息.其次,以优化功耗为目标采用改进动态规划方法进行多电压分配并构建电压岛.最后,以模拟退火算法作为搜索引擎对芯片的面积、线长和功耗进行协同优化.为减少SA迭代次数,采用了一个两阶段的降温策略.对GSRC电路的实验结果表明,该算法可获得满足边界约束的多电压布图,且和不考虑边界约束时相比,仅在功耗上平均增加5.2％.     

Deterministic VLSI block placement algorithm using Less Flexibility First principle

In this paper,a simple while effective deterministic algorithm for solving the VLSI block placement problem is proposed considering the packing area and interconnect wiring simultaneously.The algorithm is based on a principle inspired by observations of ancient professionals in solving their similar problems.Using the so-called Less Flexibility First principle,it is tried to pack blocks with the least packing flexibility on its shape and interconnect requirement to the empty space with the least packing flexibility in a greedy manner.Experimental results demonstrate that the algorithm,though simple,is quite effective in solving the problem.The same philosophy could also be used in designing efficient heuristics for other hard problems,such as placement with preplaced modules,placement with L/T shape modules,etc.     

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Multi‐voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. However, the resulted lower voltage drop noise margin brings serious obstacles in power/ground (P/G) network design of the wire‐bonding package. For voltage drop optimization, both block and power pad positions are important factors that need to be considered. Traditional multi‐voltage floorplanning methods use rough estimation to evaluate the P/G network resource without considering the locations of power pads. To remedy this deficiency, in this paper, an efficient voltage drops aware power pad assignment (PPA) method is proposed, and it is further integrated into a floorplanning algorithm. We first present a fast PPA method for each power domain by the spring model. Then, to evaluate voltage drops during floorplanning iterations, the weighted distance from the blocks to the power pads is adopted as an optimization objective instead of time‐consuming matrix computation. Experimental results on Gigascale System Research Center (GSRC) benchmark circuits indicate that the proposed method generates an optimized placement of power pads and floorplanning of blocks with high efficiency. Copyright © 2015 John Wiley & Sons, Ltd.     

Bus-driven floorplanning with thermal consideration

As the increasing number of buses in multi-core SoC designs, bus planning problems become a dominant factor in determining the chip performance. To cope with these issues, it is desirable to consider them in the early floorplanning stage. Recently, many bus-driven floorplanners have been proposed in the literature. However, these proposed algorithms only consider the bus planning problem without the thermal effect. As a result, there are hotspots, which result in high chip temperature, on the chip. In this paper, a thermal-driven bus-driven floorplanning algorithm is proposed to separate hotspots during the perturbation stage and to keep buses away from hotspots during the routing stage. To avoid time-consuming thermal simulations, the superposition of thermal profiles, which are the thermal distribution of each module, is adopted to efficiently estimate the module temperature. Compared with the state-of-the-art bus-driven floorplanner, experimental results demonstrate that the proposed algorithm can effectively separate hotspots and reduce the chip temperature.     

利用公共子序列求解固定边框布图问题

提出一种新的固定边框的布图算法．该算法采用SP表示方法,以公共子序列为基础,在随机搜索过程中限定布图宽度的变化,从而使减小芯片面积的目标与固定边框的目标在一定程度上取得一致．与现有的固定边框布图算法相比,文中算法在边框更紧凑、宽长比更大的条件下具有更高的成功率和更短的运行时间．此外,文中算法在布图初始阶段就可以对固定边框的合理性进行评估,避免了因给定的边框不合理而带来的时间上的浪费．     

考虑缺陷率模型的多项目晶圆布图规划算法

针对随机缺陷会降低多项目晶圆实际产出的问题,提出一种新的多项目晶圆布图规划算法。通过在布图规划中引入缺陷率模型的方法,增加芯片产量的裕量,降低因随机缺陷造成的产量损失。同时优化模拟退火流程,使得在布图尺寸约束条件下,布图规划过程能够跳出局部最优解陷阱。对工业实例进行布图规划的结果表明,该算法能够接受不满足布图尺寸约束条件的中间结果,从而遍历解空间,得到全局最优的布图,并且相对已有算法,使用相同数量晶圆进行切割时,算法的布图结果增加了137%的芯片产量的总裕量,同时,降低了25%的工作芯片所需要生产的晶圆数量。     

基于切分结构的快速布图规划算法

分析了切分(Slicing)结构的布图产生空白面积的原因,提出了一种直观、快速的确定模块方向的方法,改进了正则波兰表达式的一个邻域构造算子,并采用模拟退火算法实现了Slicing结构布图规划。对MCNC和GSRC的标准电路进行了测试,结果表明所提出的算法在解决Slicing结构的布图规划方面是有效的。     

Voltage island-driven multilevel floorplanning optimization algorithm

Since the existing multiple voltage floorplanning algorithms are slower and generate a higher white space, a voltage island-driven multilevel floorplanning optimization algorithm is proposed. Firstly, an ILP(Integer Linear Programming)-based approach is used to assign the voltage to each module aiming at minimizing power consumption, and all modules are divided into different voltage islands according to their voltage assignment results. Secondly, a rapid method based on enumeration and shape curve adding techniques is proposed to determine the shape and position of each voltage island. Finally, an LP(Linear Programming) model is constructed to solve the wirelength optimization problem by exchanging blocks' positions. Experimental results show that our algorithm outperforms previous methods in runtime and chip area usage ratio.     

Temporal Floorplanning Using Solution Space Smoothing Based on 3D-BSSG Structure

We develop a 3D bounded slice-surface grid (3D-BSSG) structure for representation and introduce the solution space smoothing technique to search for the optimal solution.Experiment results demonstrate that a 3D-BSSG structure based algorithm is very effective and efficient.     

A buffer planning algorithm for chip-level floorplanning

This paper studies the buffer planning problem for interconnect-centric floorplanning for nanometer technologies. The dead-spaces are the spaces left unused within a placement that are not held by any circuit block. In this paper, we proposed a buffer planning algorithm based on dead space redistribution to make good use of dead-spaces for buffer insertion. Associated with circuit blocks under topological representations, the dead space can be redistributed by moving freely some circuit blocks within their rooms in the placement. The total area and the topology of the placement keep unchanged while doing the dead space redistribution. The number of nets satisfying the delay constraint can be increased by redistributing the dead space all over the placement, which has been demonstrated by the experimental results. The increment of the number of nets that meet delay constraint is 9% on an average.