新结构MOSFET

和传统平面结构MOSFET相比，新结构MOSFET具有更好的性能(如改善的沟道效应(SCE)，理想的漏诱生势垒降低效应(DIBL)和亚阈值特性)和更大的驱动电流等。文章主要介绍了五种典型的新结构MOSFET，包括平面双栅MOSFET、FinFET、三栅MOSFET、环形栅MOSFET和竖直结构MOSFET。随着MOSFET向亚50nm等比例缩小，这些新结构器件将大有前途。     

LDD方法在提高电路工作电压中的应用研究

研究了利用轻掺杂漏结构来制作高电源电压器件的工艺方法。分析了ＬＤＤ结构参数对器件击穿特性的影响，并结合实验结果对Ｎ＾－区的注入剂量，长度及引入的串联电阻进行了优化设计。     

NMOS器件两次沟道注入杂质分布和阈电压计算

分别考虑了深浅两次沟道区注入杂质在氧化扩散过程中对表面浓度的贡献。对两次注入杂质的扩散分别提取了扩散系数的氧化增强系数、氧化衰减系数和有效杂地系数，给出了表面浓度与工艺参数之间的模拟关系式，以峰值浓度为强反型条件计算了开启电压，文章还给出了开启电压、氧化条件、不同注入组合之间的关系式。     

深亚微米MOSFET衬底电流的模拟与分析

利用器件模拟手段对深亚微米ＭＯＳＦＥＴ的衬底电流进行了研究和分析，给出了有效的道长度，栅氧厚度，源漏结深，衬底掺杂浓度以及电源电压对深亚微米ＭＯＳＦＥＴ衬底电流的影响，发现电源电压对深亚微米ＭＯＳＦＥＴ的衬底电流有着强烈的影响，热载流子效应随电源电压的降低而迅速减小，当电源电压降低到一定程度时，热载流子效应不再成为影响深亚微米ＭＯＳ电路可靠性的主要问题。     

新型高k栅介质材料研究进展

随着半导体技术的不断发展，MOSFET（metal-oxide-semiconductor field effect transistor）的特征尺寸不断缩小，栅介质等效氧化物厚度已小至nm数量级。这时电子的直接隧穿效应将非常显著，将严重影响器件的稳定性和可靠性。因此需要寻找新型高k介质材料，能够在保持和增大栅极电容的同时，使介质层仍保持足够的物理厚度来限制隧穿效应的影响。本文综述了研究高k栅介质材料的意义；MOS栅介质的要求；主要新型高k栅介质材料的最新研究动态；展望了高k介质材料今后发展的主要趋势和需要解决的问题。     

利用新型场效应管(QFET)的正向变换器

介绍了单端正向变换器基本电路，重点叙述带三路调节DC电压的100KHZ180W离线电源。它采用具有低导电阻RDS和低栅极电荷Qg的新型场效应管（QFET）作为变换电路的主开关器件，降低了电源开关损耗并提高了效率3%-5%。     

MOSFET亚阈特性分析与低温按比例缩小理论的研究

器件尺寸按比例缩小是实现超大规模集成电路的有效途径，但寄生和二级效应却将器件限在一定的水平，本文在对比分析常温与低温下小尺寸器件效应的基础上，重点研究了ＭＯＳ器件亚阈特性对器件性能及按比例缩小的影响，并根据低温工作的特点，提出了ＭＯＳ器件一种低温按比例缩小规则，该原则对低温器的优化设计，从而更大程度在提高电路与系统性能具有重要的指导意义。     

Silicon power MOSFET at low temperatures: A two-dimensional computer simulation study

Understanding how the structure of the unit-cell affects the cryogenic performance of a Si power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is an important step toward optimizing of the device for cryogenic operations. In this paper, numerical simulations of the Si power Double Diffused MOSFET’ (DMOS) are performed at room temperature and cryogenic temperatures. Physically based models for temperature dependent silicon properties are employed in the simulations. The performances of power DMOS’ with various unit-cell structures are compared at both room temperature and low temperatures. The effect of the cell structure on the on-resistance and breakdown voltage of the device are analyzed. The simulation results suggest that the device optimized for room temperature operation can be further optimized at cryogenic temperatures.     

Comparative hall measurements on wet- and dry-oxidized 4H-SiC MOSFETs

Hall measurements have been used to compare the properties of 4H-SiC inversion-mode MOSFETs with “wet” and “dry” gate oxides. While the field-effect mobilities were approximately 3–5 cm²/Vs, the Hall mobilities in 4H-SiC MOSFETs in the wet and dry oxide samples were approximately 70–80 cm²/Vs. The dry-oxidized metal oxide semiconductor field effect transistors (MOSFETs) had a higher transconductance, improved threshold voltage, improved subthreshold slope, and a higher inversion carrier concentration compared to the wet-oxidized MOSFETs. The difference in characteristics between the wet- and the dry-oxidized MOSFETs is attributed to the larger fixed oxide charge in the dry oxide sample and a higher interface trap density in the wet oxide sample.     

An analytical model for charge pumping below strong inversion and accumulation

A compact analytical model for charge pumping (CP) is derived. It accounts for emission during the high and low gate bias levels and assumes instantaneous transition edges. This model, which does not apply on the top of the CP curves when using large gate voltage swings, where emission fully proceeds during the transitions edges of the gate signal, applies on all the other regions provided that the transition times of the gate signal are much shorter than the times at steady state biases. Therefore it holds at large bias swings on both edges of Elliot curves and at small bias swings on the whole Elliot curves provided that the interface traps are completely filled [1]. It is compared with the analytical model proposed by Wachnik and Lowney [2] in which emission is not accounted for at all. This model, which holds at Elliot curve maxima when small voltage swings are used, has been shown to be extremely useful for studying interface trap properties [1, 2, 3 and 4]. The CP model proposed primarily, that of Brugler and Jespers [5], is used as a reference. The model derived in this article very satisfactorily fits the experimental curves in the regions of large CP current where it holds. Discrepancies at low current levels are due to the well-known contribution of the transistor source and drain regions or could be due to edge effects. Comparing the different models and the experimental curves allows to evaluate emission and capture during different regions of the gate bias period. The three regions of CP response, depending on the gate voltage swing and involving or not emission and the full filling of the interface traps, are also evidenced.