LPNet: A DNN based latency prediction technique for application mapping in Network-on-Chip design

Analytical models used for latency estimation of Network-on-Chip (NoC) are not producing reliable accuracy. This makes these analytical models difficult to use in optimization of design space exploration. In this paper, we propose a learning based model using deep neural network (DNN) for latency predictions. Input features for DNN model are collected from analytical model as well as from Booksim simulator. Then this DNN model has been adopted in mapping optimization loop for predicting the best mapping of given application and NoC parameters combination. Our simulations show that using the proposed DNN model, prediction error is less than 12% for both synthetic and application specific traffic. More than 108 times speedup could be achieved using DPSO with DNN model compared to DPSO using Booksim simulator.     

Protection switching schemes and mapping strategies for fail-operational hard real-time NoCs

Communication infrastructures designed for mixed-critical MPSoCs must provide isolation of traffic, hard real-time guarantees, and fault-tolerance. In previous work, we proposed the combination of protection-switching with a hybrid Time-Division-Multiplexed (TDM) and packet-switched Network-on-Chip (NoC) to achieve all three goals. In this paper, we present an FPGA implementation of such a NoC with all its features. We give synthesis results for the hybrid NoC, including the network interface, and show that our router uses over 32% fewer LUTs and registers than a competitive state-of-the-art router for mixed-critical MPSoC. We then explore different channel and task mapping strategies for critical applications which use protection switching and evaluate the effect these mappings have on the best-effort (BE) traffic in the system. Results show, that spreading out the critical traffic rather than naively dividing the system in critical and non-critical application domains is advantageous or even necessary in many cases and can allow for up to 13% more BE traffic. We give a comprehensive trade-off analysis of three protection switching schemes—1:n, 1:1, and 1+1—and show that 1+1 protection has less than half the worst case latency for critical traffic that 1:n and 1:1 protection have. At the same time, 1+1 protection, on average, only causes a 1.18% earlier saturation rate for BE traffic, which we consider to be affordable. We conclude that 1+1 protection is ideally suited for use in mixed-critical systems with high safety requirements.     

基于云自适应遗传算法的NoC路径分配研究

路径分配是NoC设计流程中的两个关键步骤之一;路径分配的结果对NoC系统的性能尤其是通讯延时有着很重要的影响;多约束条件下的NoC路径分配问题是NP完全问题,要求出其最优解比较困难,目前常用的方法是利用启发式算法求得其较优解;文中提出一种基于云自适应遗传算法的NoC路径分配解决方案,该算法利用云模型对传统遗传算法加以改进,采取新的方法自动调整遗传算法过程中的交叉概率pc和变异概率pm,将适应度与云模型的3个参数Ex、En、He相互结合,从而达到优化遗传算法的目的;将此算法应用于2D-Mesh拓扑结构的NoC中,以平衡链路负载和联合优化为实验目标,以优化静态通讯分配结果;实验证明,文章所采取的算法在平衡链路负载和联合优化方面均取得了良好的效果。     

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

This paper proposes a novel QoS-aware and congestion-aware Network-on-Chip architecture that not only enables quality-oriented network transmission and maintains a feasible implementation cost but also well balance traffic load inside the network to enhance overall throughput. By differentiating application traffic into different service classes, bandwidth allocation is managed accordingly to fulfill QoS requirements. Incorporating with congestion control scheme which consists of dynamic arbitration and adaptive routing path selection, high priority traffic is directed to less congested areas and is given preference to available resources. Simulation results show that average latency of high priority and overall traffic is improved dramatically for various traffic patterns. Cost evaluation results also show that the proposed router architecture requires negligible cost overhead but provides better performance for both advanced mesh NoC platforms.     

MoNoC: A monitored network on chip with path adaptation mechanism

Complex systems on chip containing dozens of processing resources with critical communication requirements usually rely on the use of networks on chip (NoCs) as communication infrastructure. NoCs provide significant advantages over simpler infrastructures such as shared busses or point to point communication, including higher scalability, more efficient energy management, higher bandwidth and lower average latency. Applications running on NoCs with more than 10% of bandwidth usage attest that the most significant portion of message latencies refers to buffered packets waiting to enter the NoC, whereas the latency portion that depends on the packet traversing the NoC is sometimes negligible. This work presents an adaptive routing architecture, named Monitored NoC (MoNoC), which is based on a traffic monitoring mechanism and the exchange of high priority control packets. This method enables to adapt paths by choosing less congested routes. Practical experiments show that the proposed path adaptation is a fast process, enabling to transmit packets with smaller latencies, up to 9 times smaller, by using non-congested NoC regions.     

特定应用片上网络的研究综述

特大规模集成电路技术的飞速发展,使得把大量的知识产权（Intellectual Property,IP）核集成到单一的芯片上形成的片上系统成为了今后微电子发展的主流趋势。片上系统面临着许多设计和制造问题,片上网络为解决片上系统的这些问题提供一种行之有效的方案。当前及今后的片上系统都主要面向特定应用或特定应用类,因此,片上网络也是面向特定应用的片上网络,对特定应用片上系统面临的问题、特定片上网络的提出、发展、和主要研究内容进行综述。     

一种面向2D-Mesh拓扑结构的片上网络容错路由算法设计与分析

介绍了片上网络的拓扑结构和路由算法和故障模型,提出了一种适用于NoC 2D-Mesh结构的容错性路由算法,可以根据邻居节点的状态动态的选择路由。通过仿真证明了在均匀随机流量模式下,相对于XY路由算法,使用该算法吞吐量更高,平均端到端时延更小。     

基于3D Mesh结构的一种静态路由算法

3D NoC在同构多核系统中相比2D NoC具有更为优越的性能.本文在研究3D Mesh结构的基础上,对拓扑结构中的平均延时和理想吞吐量进行了理论上的评估,并提出了一种基于3D Mesh的新的静态路由算法,最后运用NS2网络仿真软件对其进行仿真和比较.实验结果显示,新的路由算法可以有效地提高吞吐量,并在大规模数据传输时...     

片上网络带宽资源QoS调度算法

提出一种片上网络带宽资源QoS调度算法。通过分布式地动态调整有保障服务(GS)连接在每个路由器中的优先级,解决共享同一物理链路的不同GS连接之间的传输冲突问题,从而保障时延、带宽和时延抖动等QoS。通过给尽力而为服务(BE)通道分配动态优先级和监控GS流量2种方法的应用,有效提高了BE数据流的服务质量及链路利用率。     

CAFES: A framework for intrachip application modeling and communication architecture design

This paper describes CAFES, an extensible, open-source framework supporting several tasks related to high-level modeling and design of applications employing complex intrachip communication infrastructures. CAFES comprises several built-in models, including application, communication architecture, energy consumption and timing models. It also includes a set of generic and specific algorithms and additional supporting tools, which jointly with the cited models allow the designer to describe and evaluate applications requirements and constraints on specified communication architectures. Several examples of the use of CAFES underline the usefulness of the framework. Some of these are approached in this paper: (i) a realistic application captured at high-level that has its computation time estimated after mapping at the clock cycle level; (ii) a multi-application system that is automatically mapped to a large intrachip network with related tasks occupying contiguous areas in the chip layout; (iii) a set of mapping algorithms explored to define trade-offs between run time and energy savings for small to large intrachip communication architectures.