Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

软件集成测试技术研究

首先分析了集成测试的原理和特点，并指出了集成测试的重要性。然后结合传统软件与面向对象软件开发的方法和技术，详细介绍了传统软件的集成测试方法和策略，并深入分析了面向对象软件集成测试的原理和方法。     

异构数据集成方法研究与实现

为解决异构数据集成的复杂性问题，文章提出了一种异构数据同步的新方法——半集成式中间件法。该方法成功地应用在重庆市社会保障综合信息系统中，具有易于实现、可扩展性、跨平台性和效率高等特点。     

在协议集成测试系统上开展路由协议测试

在分析路由协议的特性及其测试需求的基础上，提出利用窗口黑盒来描述被测协议，利用多通道测试方法扩展对被测实现的控制和观察，通过扩充参考实现增强系统的测试能力。将这些理论，技术应用于系统中，对路由协议开展了有效的测试活动，为国产高性能路由器的开发提供了有力的支持，也进一步增强了PITS系统的功能和适用性。     

一种动态开关电容运算放大器共模负反馈电路

本文主要介绍了一种应用于Cascode结构运放中的开关电容共模负反馈电路，它具有稳定性好、对运放频率特性影响小、不消耗额外功率等优点。对电路运用Hspice进行了模拟，并给出了模拟结果。     

美国钢铁企业的并购浪潮及特点分析

介绍了最近美国大型钢铁企业发生的主要并购活动。并对这些并购活动的特点进行了分析。     

STI process steps for sub-quarter micron CMOS

This paper presents Shallow Trench Isolation (STI) process steps for sub-1/4 μ CMOS technologies. Dummy active areas, vertical trench sidewalls, excellent gap filling, counter mask etch step and CMP end point detection, have been used for a 0.18 μm CMOS technology. Electrical results obtained with a 5.5 nm gate oxide thickness show good isolation down to 0.3 μm spacing. Good transistor performances have been demonstrated.     

Strategic appraisal of energy models for Mozambique

The needs that an energy supply system must meet are constantly changing, due to technological, social and political reasons. Effective energy planning is a dynamic process that is repeated periodically and adjusts to changing conditions. Energy decision makers and planners are no longer able to rely on inductive decision making since they have to investigate the effect of various decision parameters and possible future changes. To help in this process, models have been developed where estimates of future load growth, candidate power plants, fuels and other key factors can be introduced, from which the planners can evaluate decision parameters and the available alternatives. The paper presents the different methodologies and practices that are used by 11 energy models for energy demand forecasting, supply side management and generation expansion planning, demand side management and integrated resource planning. The paper concludes to the presentation of a strategic appraisal of the examined energy models appropriate for energy planning in Mozambique. Three models are proposed for conducting demand forecasting, generation expansion planning and demand side management. Copyright © 2002 John Wiley & Sons, Ltd.     

舰艇电子战综合对抗系统应用探讨

通过对现代海上电子战特点深刻探讨。分析了现代海战条件对舰船电子战对抗能力需求。并对现代舰船电子战综合对抗系统所采用的新技术情况进行探讨。     

Layout-Specific Circuit Evaluation in 3-D Integrated Circuits

In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit evaluation, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D.