A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM

In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.     

以CGA卡为基础的智能显示系统

本文介绍了以微处理器与ＩＢＭ－ＰＣ上的彩色／图形适配器相结合构成的一种智能显示系统。本系统主要解决数控系统中主ＣＰＵ与６８４５ＣＲＴＣ争夺显示缓存的矛盾。保证了６８４５ＣＲＴＣ对显示缓存操作的时间要求；并且保证了数控系统中主ＣＰＵ对显示缓存操作的随意性。     

Trade-offs in scan path and BIST implementations for RAMs

In this article we propose efficient scan path and BIST schemes for RAMs. Tools for automatic generation of these schemes have been implemented. They reduce the design effort and thus allow the designer to select the more appropriate scheme with respect to various constraints.     

一种高性能图形板的设计与实现

介绍了一种采用高性能嵌入式图形处理器、大容量双端口视频存储器、高性能查色表以及超大规模可编程逻辑器件设计的图形显示控制板的基本组成和工作原理。     

内嵌RAM的液晶显示控制驱动器

讨论一种液晶控制驱动器的设计及使用方法。根据设计要求，阐述了每个分模块的设计思想与设计方法，并进行了数模混合仿真。     

基于FPGA的高速数据存储系统优化设计

针对遥测系统数据记录装置中数据传输速率与存储速率不匹配的问题,提出Flash的并行存储方案,采用交替双平面的编程方式可以使得存储器的存储速率达到单片Flash最高存储速率的2倍,即60 MB/s;对控制单元FPGA内部双端口RAM的逻辑设计进行改进,解决了数据存储异常的现象。在数据回收方面,提出了多备份的设计思想和备用读数接口的设计方案,已在工程应用中得到成功实践,验证了该数据记录装置的可靠性。     

Event-driven,pattern-based methodology for cost-effective development of standardized personal health devices

Experiences applying standards in personal health devices (PHDs) show an inherent trade-off between interoperability and costs (in terms of processing load and development time). Therefore, reducing hardware and software costs as well as time-to-market is crucial for standards adoption. The ISO/IEEE11073 PHD family of standards (also referred to as X73PHD) provides interoperable communication between PHDs and aggregators. Nevertheless, the responsibility of achieving inexpensive implementations of X73PHD in limited resource microcontrollers falls directly on the developer. Hence, the authors previously presented a methodology based on patterns to implement X73-compliant PHDs into devices with low-voltage low-power constraints. That version was based on multitasking, which required additional features and resources. This paper therefore presents an event-driven evolution of the patterns-based methodology for cost-effective development of standardized PHDs. The results of comparing between the two versions showed that the mean values of decrease in memory consumption and cycles of latency are 11.59% and 45.95%, respectively. In addition, several enhancements in terms of cost-effectiveness and development time can be derived from the new version of the methodology. Therefore, the new approach could help in producing cost-effective X73-compliant PHDs, which in turn could foster the adoption of standards.     

无源LC传感器信号读取系统扫频源设计

针对连续快速的高频线性扫频信号源在无源LC传感器信号读取中的应用需求,设计并实现了0~400 MHz任意频率段的线性扫频源系统;该系统的核心器件为直接数字频率合成器(DDS)AD9910,采用该芯片的RAM模式和数字斜坡模式,详细介绍各模式工作原理及寄存器的具体配置过程,并分别以这两种模式实现了输出扫频信号;测试结果表明,两种方式均可实现高频高速捷变稳定信号的连续扫频;该扫频源具有高精度、稳定性好、频率捷变快和小型化的等特点,为LC传感器的工程应用提供了技术基础。     

Subquadratic Algorithms for 3SUM

We obtain subquadratic algorithms for 3SUM on integers and rationals in several models. On a standard word RAM with w-bit words, we obtain a running time of . In the circuit RAM with one nonstandard AC ⁰ operation, we obtain . In external memory, we achieve O(n ²/(MB)), even under the standard assumption of data indivisibility. Cache-obliviously, we obtain a running time of . In all cases, our speedup is almost quadratic in the “parallelism” the model can afford, which may be the best possible. Our algorithms are Las Vegas randomized; time bounds hold in expectation, and in most cases, with high probability.