360-μW 4.1-dB NF CMOS MedRadio receiver RF front-end with current-reuse Q-boosted resistive feedback LNA for biomedical IoT applications

In this paper, a low-power low-noise complementary metal-oxide semiconductor (CMOS) receiver RF front-end (RFFE) that employs a current-reuse Q-boosted resistive feedback low-noise amplifier (RFLNA) is proposed for 401 to 406 MHz medical device radio-communication service band IoT applications. By employing a series RLC input matching network, the proposed RFLNA has the advantages of both the conventional RFLNA and the inductively degenerated common-source LNA without using large on-chip spiral inductors at the sources of the main transistors. The proposed active mixer utilizes a current-reuse transconductor, in which a p-channel metal-oxide semiconductor (PMOS) transistor performs a current-bleeding function to reduce direct current (DC) and flicker noise in the switching stage of the active mixer. The proposed receiver RFFE is implemented in a 65-nm CMOS process and achieves a voltage gain of 30.9 dB, noise figure of 4.1 dB, S11 of less than −10 dB, and IIP3 of −22.9 dBm. It operates at a supply voltage of 1 V with bias currents of 360 μA. The active die area is 0.4 mm × 0.35 mm.     

Evaluation of Gene Expression Knock-Down by Chemically and Structurally Modified Gapmer Antisense Oligonucleotides

We analyzed the effect of modified nucleotides within gapmer antisense oligonucleotides on RNase H mediated gene silencing. Additionally, short hairpins were introduced into antisense oligonucleotides as structural motifs, and their influence on biological and physicochemical properties of pre-structured gapmers was investigated for the first time. The results indicate that two LNA residues in specified positions of the gap flanking regions are sufficient and favorable for efficient knock-down of the β-actin gene. Furthermore, the introduction of other modified nucleotides, i. e. glycyl-amino-LNA−T, 2′-O-propagyluridine, polyamine functionalized uridine, and UNA, in specified positions, also increases the inhibition of β-actin expression. Importantly, the presence of hairpins within the gapmers improves their silencing properties.     

5.8GHzWiMAX低噪声放大器设计与仿真

介绍了一种基于IEEE802.16标准的高频段WiMAX低噪声放大器(LNA)的设计方法,工作频段在5.8 GHz,采用稳 茂0.15 μm pHEMT工艺4×50 μm晶体管大信号模型,选用Current-Reused结构作为LNA电路结构,并优化设计LNA的电路 偏置电路.利用Agilent公司的 ADS2008 ...     

基于薄膜工艺的x波段下变频器设计

本文介绍了一个基于薄膜电路工艺设计、加工的X波段下变频器.首先对整体方案进行分析论证,然后运用安捷伦公司的ADS仿真设计软件,对射频及中频滤波器、朗格电桥、低噪声放大器和混频器等电路单元及变频器系统进行了仿真设计.最后经过加工测试验证,该变频器性能指标良好.其工作频率为9.35GHz - 9.85GHz,变频增益≥26dB,噪声系数≤2dB,P01dB压缩点功率≥10dBm,输入、输出驻波≤1.3,镜像抑制比≥50dB;本振输入为0±1dBm.整个电路腔体结构尺寸为70mm×20mm×10mm.     

适用于GSM900/GPS系统的双频段低噪声放大器设计

基于SMIC 0.18μm CMOS工艺,设计了一个适用于GSM900和GPS系统的并行式双频段低噪声放大器.电路采用1.8V电源供电,考虑到两级之间的匹配特性,运用了级间电感技术.介绍了输入、输出匹配电路的具体设计方法.运用Cadence中的SpectreRF软件进行仿真,结果表明,增益特性S21在两个频段均大于10...     

一种0.18μm CMOS 全集成直接变频数字卫星调谐器

本文设计了一种满足DVB-S/S2和ABS-S标准的全集成直接变频数字卫星调谐芯片。具有单端转差分功能的低噪声放大器及无源混频器实现了高线性度与低噪声的射频前端,同时频率综合器集成了环路滤波器有效地提高了集成度及减小系统成本与板级调试时间。0.18μm CMOS工艺制程下,PCB板级测试结果表明芯片在900至2150 MHz 的L波段上噪声系数小于7.6 dB,4.42 M符号率 QPSK-3/4 模式下的灵敏度达到-91dBm。全集成整数频率综合器在2150到4350 MHz的工作频带内相位误差小于1°。芯片集成LDO,外部电源电压3.3V,工作电流145mA。     

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.     

An energy detection receiver for non-coherent IR-UWB

A non-coherent receiver for impulse radio ultra-wide band(IR-UWB)is presented.The proposed receiver front-end consists of a high gain LNA,a high frequency detector and an intermediate frequency(IF)amplifier to amplify the recovered signal and drive an external test instrument.To meet the requirements of high gain and a low noise figure(NF)under moderate power consumption for the LNA,capacitor cross coupled(CCC)and current reuse techniques were adopted.The detector consists of a squarer and an integrator.The overall circuit consumes 41.2mA current with a supply voltage of 1.8 V at a 400 MHz pulse rate.The resulting energy efficiency is 0.19 nJ/pulse.A chip prototype is implemented in 0.18-μm CMOS.The die area is 2.1×1.4 mm~2 and the active area is 1.7×0.98 mm~2.     

A differential low-voltage high gain current-mode integrated RF receiver front-end

A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed.It contains a differential transconductance low noise amplifier（G_m-LNA） and a differential current-mode 0 down converted mixer.The single terminal of the G_m-LNA contains just one MOS transistor,two capacitors and two inductors.The gate-source shunt capacitors,C_x1 and C_x2,can not only reduce the effects of gate-source C_gs on resonance frequency and input-matching impedance,but they also enable the gate inductance L_g1,2 to be selected at a very small value.The current-mode mixer is composed of four switched current mirrors.Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end.The RF front-end operates under 1 V supply voltage.The receiver RFIC was fabricated using a chartered 0.18μm CMOS process.The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point（IIP3） of-7.02 dBm.The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations.     

采用balun低噪声放大器的5GHz 7.2-dB NF低功耗直接转换接收机前端电路

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm². It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.