Application-aware virtual paths insertion for NOCs

Network-on-chip (NoC) has rapidly become a promising alternative for complex system-on-chip architectures including recent multicore architectures. Additionally, optimizing NoC architectures with respect to different design objectives that are suitable for a particular application domain is crucial for achieving high-performance and energy-efficient customized solutions. Despite the fact that many researches have provided various solutions for different aspects of NoCs design, a comprehensive NoCs system solution has not emerged yet. This paper presents a novel methodology to provide a solution for complex on-chip communication problems to reduce power, latency and area overhead. Our proposed NoC communication architecture is based on setting up virtual source–destination paths between selected pairs of NoCs cores so that the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these virtual paths. In this scheme, the paths are constructed for an application based on its task-graph at the design time. After that, the run time scheduling mechanism is applied to improve the buffer management, virtual channel and switch allocation schemes and hence, the constructed paths are optimized dynamically. Moreover, in our design the router complexity and its overheads are reduced. Additionally, the suggested router has been implemented on Xilinx Virtex-5 FPGA family. The evaluation results captured by SPLASH-2 benchmark suite reveal that in comparison with the conventional NoC router, the proposed router takes 25% and 53% reduction in latency and energy, respectively besides 3.5% area overhead. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and total power consumption with negligible area overhead.     

Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip

This paper proposes a novel QoS-aware and congestion-aware Network-on-Chip architecture that not only enables quality-oriented network transmission and maintains a feasible implementation cost but also well balance traffic load inside the network to enhance overall throughput. By differentiating application traffic into different service classes, bandwidth allocation is managed accordingly to fulfill QoS requirements. Incorporating with congestion control scheme which consists of dynamic arbitration and adaptive routing path selection, high priority traffic is directed to less congested areas and is given preference to available resources. Simulation results show that average latency of high priority and overall traffic is improved dramatically for various traffic patterns. Cost evaluation results also show that the proposed router architecture requires negligible cost overhead but provides better performance for both advanced mesh NoC platforms.     

片上网络路由算法综述

从具有不同自适应度的无关(oblivious)路由和自适应(adaptive)路由两方面对适用于片上网络的路由算法进行总结和分析,从所适用的拓扑结构、是否防止死锁等方面对算法进行评价,并提出片上网络路由算法研究的方向。     

片上网络中有保障服务的性能评估

本文针对如何评测片上网络中的有保障服务(Guaranteed-Services,GS)对尽力而为(Best-Effort,BE)流量的传输性能的影响进行了研究,提出了评测重点及相关性能指标,给出了构建网络流量的方法,采用了一种分层逐级抽象的方法搭建了支持任意拓扑结构、任意规模、多种网络协议的性能评估平台,实现了对片上网络中GS服务的性能评估.评测实例的结果表明该平台达到了评价片上网络中GS服务的服务质量和分析GS服务对网络整体性能的影响的目的,有效的帮助设计者在保障局部服务质量的同时提高网络性能,为设计优化提供了依据.     

Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching

Multicast on-chip communication is encountered in various cache-coherence protocols targeting multi-core processors, and its pervasiveness is increasing due to the proliferation of machine learning accelerators. In-network handling of multicast traffic imposes additional switching-level restrictions to guarantee deadlock freedom, while it stresses the allocation efficiency of Network-on-Chip (NoC) routers. In this work, we propose a novel partitioned NoC router microarchitecture, called SmartFork, which employs a versatile and cost-efficient multicast packet replication scheme that allows the design of high-throughput and low-cost NoCs. The design is adapted to the average branch splitting observed in real-world multicast routing algorithms. Compared to state-of-the-art NoC multicast approaches, SmartFork is demonstrated to yield high performance in terms of latency and throughput, while still offering a cost-effective implementation.     

基于双维序路由策略的低能耗NoC网络分配

在片上网络(NoC)的网络分配与任务映射相配合的路径分配中,单维序路由策略会限制可行解空间。为此,提出一种基于双维序路由策略的网络分配方法。在路径分配步骤中采用双维序路由法,设计以带宽、延时和无死锁为约束条件、以降低动态及静态能耗为优化目标的遗传算法。实验结果表明,该方法可以扩大任务映射的可行解空间,求解最小所需带宽比单维序法平均减少6.3%,且在各种带宽场合时均能求得更低能耗解。     

3D floorplanning of low-power and area-efficient Network-on-Chip architecture

Network-on-Chip (NoC) architectures have been adopted by chip multi-processors (CMPs) as a flexible solution to the increasing delay in the deep sub-micron regime. However, the shrinking feature size limits the performance of NoCs due to power and area constraints. In this paper, we propose three 3D floorplanning methods for a Triplet-based Hierarchical Interconnection Network (THIN) which is a new high performance NoC. The proposed floorplanning methods use both Manhattan and Y-architecture routing architectures so as to improve the performance, reduce the power consumption and area requirement of THIN. A cycle accurate simulator was developed based on Noxim NoC simulator and ORION 2.0 energy model. The proposed floorplanning methods show up to 24.69% energy and 8.84% area reduction at best compared with 3D Mesh. Our analysis concludes that THIN is not only a feasible but also a low-power and area-efficient NoC at physical level.     

A study of 3D Network-on-Chip design for data parallel H.264 coding

In this paper, we implement, analyze and compare different Network-on-Chip (NoC) architectures aiming at higher efficiencies for MPEG-4/H.264 coding. Two-dimensional (2D) and three-dimensional (3D) NoCs based on Non-Uniform Cache Access (NUCA) are analyzed. We present results using a full system simulator with realistic workloads. Experiments show the average network latencies in two 3D NoCs are reduced by 28% and 34% respectively, comparing with 2D design. It is also shown that heat dissipation is a trade-off in improving performance of 3D chips. Our analysis and experiment results provide a guideline to design efficient 3D NoCs for data parallel H.264 coding applications.     

Congestion-aware ant colony based routing algorithms for efficient application execution on Network-on-Chip platform

Networks-on-Chip (NoC) is an interesting option in design of communication infrastructures for embedded systems. It provides a scalable structure and balanced communication between the cores. Parallel applications that take advantage of the NoC architectures, are usually are communication-intensive. Thus, a big deal of data packets is transmitted simultaneously through the network. In order to avoid congestion delays that deteriorate the execution time of the implemented applications, an efficient routing strategy must be thought of carefully. In this paper, the ant colony optimization paradigm is explored to find and optimize routes in a mesh-based NoC. The proposed routing algorithms are simple yet efficient. The routing optimization is driven by the minimization of total latency during packets transmission between the tasks that compose the application. The presented performance evaluation is threefold: first, the impact of well-known synthetic traffic patterns is assessed; second, randomly generated applications are mapped into the NoC infrastructure and some synthetic communication traffics, that follow known patterns, are used to simulate real situations; third, sixteen real-world applications of the E3S and one specific application for digital image processing are mapped and their execution time evaluated. In both cases, the obtained results are compared to those obtained with known general purpose algorithms for deadlock free routing. The comparison avers the effectiveness and superiority of the ant colony inspired routing.     

一种无缓存片上网络交叉开关调度机制

提出一种无缓存片上网络的交叉开关调度机制.无缓存是指将路由节点输入端口缓存以及相应的控制逻辑移除,以降低实现开销.该调度机制在每个输入端口设置一条自回环通道,并在“偏转”路由基础上采用一种基于“偏转”和自回环次数的优先级策略,以通过减小“偏转”次数提高无缓存片上网络的网络性能.实验表明,此调度机制相对于基本的无缓存机制,可保证在硬件开销与能耗不增的前提下,提高网络性能;相对于典型的有缓存机制,在负载较低时其网络性能更优,负载较高时性能略低,但可使硬件开销与能耗分别下降58.9％与40.2％,并使频率提高74.6％.