A pseudo‐differential current‐reuse structure for opamp‐sharing pipelined analog‐to‐digital converters

In this paper, a power efficient pseudo‐differential (PD) current‐reuse structure is presented to alleviate the memory effects of opamp‐sharing in pipelined analog‐to‐digital converters. To implement the PD current‐reuse structure, a switched‐capacitor circuit is introduced for multiplying digital‐to‐analog converter, which has a slight modification compared with the conventional switching scheme with no power penalty. In the proposed multiplying digital‐to‐analog converter circuit, the common‐mode offset amplification of the PD structures is eliminated. Moreover, a PD current‐reuse amplifier is developed from the telescopic structure with an inverter‐based gain‐boosting circuit. The effectiveness of the proposed structure is evaluated in comparison with existing current‐reuse techniques. Copyright © 2014 John Wiley & Sons, Ltd.     

Evaluation of the pole expressions of nano-scale multistage amplifiers based on equivalent output impedance

Several frequency compensation schemes have been proposed to stabilize multistage amplifiers with negative feedback. The performance of these amplifiers can be analyzed by inspecting their input-output transfer function as representation of their frequency response. With many circuit elements affecting the output response, it is relatively difficult to obtain the real transfer function of multistage amplifiers based on only the original small-signal expressions. Instead, certain techniques such as Miller’s theorem are used to approximate important parameters such as DC gain and dominant pole. These methods are not generally helpful for approximating the nondominant poles which have a critical role on the loop stability of nano-scale amplifiers. With this issue in mind, this work proposes a systematic methodology to achieve the pole expressions of multistage amplifiers with frequency compensation. The key in the proposed technique is to model the equivalent impedance of the compensation loop at the output. The effectiveness of the proposed approach has been verified through comparison between the transfer functions obtained from theory and those transfer functions found in the literature.     

A reconfigurable two-stage cyclic ADC for low-power applications in 3.3 V 0.35 µm CMOS

This article presents a reconfigurable pipeline analog-to-digital converter (ADC) using a two-stage cyclic configuration. The ADC consists of two stages with 1.5 effective bit resolution, two reference circuits for voltage and current biasing, and a clock generator and timing circuit. Throughout the development of this ADC, several techniques were combined for reducing the power consumption as well as for preserving the converter linearity. To reduce the power consumption, the circuit has a single operational trans-conductance amplifier shared by both pipeline stages. To keep conversion linearity, circuits such as the bootstrapped complementary metal-oxide semiconductor (CMOS) transmission gates and a robust comparator topology were implemented. The circuit can be configured to perform conversion between 7 and 15 bit resolutions, and it works with the master clock frequency in the range of 1 kHz to 40 MHz. The circuit has been prototyped in a 3.3 V 0.35 µm CMOS process and consumes 14.1 mW at 40 MHz and 8 MSample/s sampling rate. With this resolution and sampling rate, it achieves 60.1 dB SNR, 56.57 dB SINAD and 9.1 bit ENOB at 0.666 MHz input frequency and 53.6 dB SNR, 52.4 dB SINAD and 8.6 bit ENOB at 3.85 MHz input frequency. The technological FOM obtained was 13.2 A s/m².     

A Switched Opamp-Based Bandpass Filter: Design and Implementation in a 0.35 μm CMOS Technology

A fully differential SC bandpass filter (central frequency, 58 kHz; Q = 15; and voltage gain, 8) based on the switched-opamp approach is designed and implemented in this work. The filter operates from a single 1 V supply voltage and is realized in a 0.35 m CMOS technology. It has been characterized with a sampling frequency of 1 MHz and its power consumption is about 230 W. As a main internal filter component, an appropiate switched opamp was also designed. Its common-mode feedback circuit was implemented by using an error amplifier and sampling of the output common-mode voltage is carried out by applying a DC offset to level shift the common-mode sample. It provides an accurate common-mode output for a wide temperature and supply voltage ranges.     

一种带有增益提高技术的高速CMOS运算放大器设计

设计了一种用于高速ADC中的高速高增益的全差分CMOS运算放大器。主运放采用带开关电容共模反馈的折叠式共源共栅结构,利用增益提高和三支路电流基准技术实现一个可用于12~14 bit精度,100 MS/s采样频率的高速流水线（Pipelined）ADC的运放。设计基于SMIC 0.25μm CMOS工艺,在Cadence环境下对电路进行Spectre仿真。仿真结果表明,在2.5 V单电源电压下驱动2 pF负载时,运放的直流增益可达到124 dB,单位增益带宽720 MHz,转换速率高达885 V/μs,达到0.1%的稳定精度的建立时间只需4 ns,共模抑制比153 dB。     

Hybrid cascode feedforward compensation for nano-scale low-power ultra-area-efficient three-stage amplifiers

A modified frequency compensation technique is proposed for low-power area-efficient three-stage amplifiers driving medium to large capacitive loads. Coined hybrid cascode feedforward compensation (HCFC), the total compensation capacitor is divided and shared between two internal high-speed feedback loops instead of only one loop as is common in prior art. Detailed analysis of this technique shows significant improvement in terms of bandwidth and stability. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30% and 40% respectively, compared to the prevailing schemes.     

A 12 bit 100 MS/s pipelined analog to digital converter without calibration

A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter(ADC) in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC's linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumpt...     

一种无运放电流模式带隙基准设计

为满足集成电路中低功耗／低温度系数的要求,基于负反馈钳位原理,采用分段线性补偿技术,通过在高低温度段分别插入非线性电流修正项对基准进行了曲率补偿,得到一种新型的无需运放的曲率补偿电流模式带隙电压基准源。仿真得到典型工艺下电路在室温27℃,工作电压4．5V下输出电压1．25062V,工作电流小于38pA,功耗小于170μW。在-40～＋150℃。宽温度范围内,基准电压在1．25018～1．25086V之间变化,温度系数约为2．86ppm／℃。     

New universal biquad filters using only two unity-gain cells

New current-mode and voltage-mode universal biquad filters are presented using only two unity-gain cells (one current follower and one voltage follower) in each configuration. The proposed filters employ one less follower than in the literature to date. The filters can realize highpass, bandpass, lowpass, notch and allpass responses without any changes in the circuit topology. The circuits enjoy the following advantages: minimum number of active elements, no component-matching condition and low active and passive sensitivities.     

Relationship between settling time and pole–zero placements for three-stage CMOS opamp

In this article, the effect of pole–zero placements on settling time has been analysed for a three-stage CMOS operational amplifier (opamp) with nested Miller compensation (NMC) and reversed nested Miller compensation (RNMC) schemes. In this study, optimised balancing of speed and power is done for a three-stage CMOS opamp for a given load condition (on-chip opamp). Optimum values of circuit parameters have been derived for power efficient shifting of poles and zeros. The effect of placement of poles and zeros on dynamic settling error (DSE) is analysed by means of numerical simulation using MATLAB. This analysis will be useful to ascertain the relationship between pole–zero placements and settling time. The study of the effects of compensation elements on pole–zero placements has been done to assist the circuit designers to achieve better performance. Analysis of the effect of capacitive load on pole–zero placements and DSE has been done in this study. A technique has been developed to find out the upper and lower limits of compensation capacitor that allows fast settling with low power. The validity of the analytical work has been checked by simulation using Tanner tool in 0.35-µm CMOS technology. In the case of RNMC scheme, a power dissipation of 60.17?µw and a settling time of 340?ns are achieved; the results obtained are better than the earlier reported design technique. In the case of NMC, the simulation has been done to validate the analytical analysis.