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1.
Crashworthiness simulation system is one of the key computer-aided engineering (CAE) tools for the automobile industry and implies two potential conflicting requirements: accuracy and efficiency. A parallel crashworthiness simulation system based on graphics processing unit (GPU) architecture and the explicit finite element (FE) method is developed in this work. Implementation details with compute unified device architecture (CUDA) are considered. The entire parallel simulation system involves a parallel hierarchy-territory contact-searching algorithm (HITA) and a parallel penalty contact force calculation algorithm. Three basic GPU-based parallel strategies are suggested to meet the natural parallelism of the explicit FE algorithm. Two free GPU-based numerical calculation libraries, cuBLAS and Thrust, are introduced to decrease the difficulty of programming. Furthermore, a mixed array and a thread map to element strategy are proposed to improve the performance of the test pairs searching. The outer loop of the nested loop through the mixed array is unrolled to realize parallel searching. An efficient storage strategy based on data sorting is presented to realize data transfer between different hierarchies with coalesced access during the contact pairs searching. A thread map to element pattern is implemented to calculate the penetrations and the penetration forces; a double float atomic operation is used to scatter contact forces. The simulation results of the three different models based on the Intel Core i7-930 and the NVIDIA GeForce GTX 580 demonstrate the precision and efficiency of this developed parallel crashworthiness simulation system. 相似文献
2.
Two-dimensional digital image correlation (2D-DIC) is an experimental technique used to measure in-plane displacement of a test specimen. Real-time measurement of full-field displacement data is challenging due to enormous computational load of the algorithm. In order to improve the computational speed, the focus of recent research works has been on the approach of parallelization across subsets within image pairs using graphics processing unit (GPU). But alternate GPU-based parallelization approaches to improve the performance of this algorithm as per the order of data processing have not been explored. To address this research gap, our method utilizes parallelism within a subset as well as across subsets for each computation step in an iteration cycle. A heterogeneous (CPU-GPU) framework in combination with a pyramid-based initial values estimation for subsets (in parallel) is proposed in this work. The precompute steps of the proposed framework are implemented using CPU, whereas the main iterative steps are realized using GPU. It is demonstrated that the overall computational speed of the proposed heterogeneous framework improves by compared to a sequential CPU-based implementation for a pair of gray-scale images with a resolution of pixels. As an important milestone, feasibility to measure deformations in real time ( 1 s) is manifested in this study. 相似文献
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We discuss the efficiency of parallelization on graphical processing units (GPUs) for the simulation of the one-dimensional Potts model with long-range interactions via parallel tempering. We investigate the behavior of some thermodynamic properties, such as equilibrium energy and magnetization, critical temperatures as well as the separation between the first- and second-order regimes. By implementing multispin coding techniques and an efficient parallelization of the interaction energy computation among threads, the GPU-accelerated approach reached speedup factors of up to 37. 相似文献
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Graphics processing unit (GPU) has been applied successfully in many computation and memory intensive realms due to its superior performances in float-pointing calculation, memory bandwidth and power consumption, and has great potential in power system applications. Contingency screening is a major time consuming part of contingency analysis. In the absence of relevant existing research, this paper is the first of its kind to propose a novel GPU-accelerated algorithm for direct current (DC) contingency screening. Adapting actively unique characteristics of GPU software and hardware, the proposed GPU algorithm is optimized from four aspects: data transmission, parallel task allocation, memory access, and CUDA (Compute Unified Device Architecture) stream. Case studies on a 3012-bus system and 8503-bus system have shown that the GPU-accelerated algorithm, in compared with its counterpart CPU implementation, can achieve about 20 and 50 times speedup respectively. This highly promising performance has demonstrated that carefully designed performance tuning in conjunction with GPU programing architecture is imperative for a GPU-accelerated algorithm. The presented performance tuning strategies can be applicable to other GPU applications in power systems. 相似文献
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近几年图形处理器GPU的通用计算能力发展迅速,现在已经发展成为具有巨大并行运算能力的多核处理器,而CUDA架构的推出突破了传统GPU开发方式的束缚,把GPU巨大的通用计算能力解放了出来.本文利用GPU来加速AES算法,即利用GPU作为CPU的协处理器,将AES算法在GPU上实现,以提高计算的吞吐量.最后在GPU和CPU... 相似文献
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为了提高光照不均图像的增强速率,提出了基于GPU平台的同态滤波并行算法.根据同态滤波算法的并行性,利用CUDA软硬件体系架构,实现了同态滤波算法向GPU上的移植.利用多幅不同分辨率图像作为测试数据,对比CPU和GPU方案的计算效率.实验结果表明,GPU实现方案大幅度提升了计算效率. 相似文献
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Cris Cecka Adrian J. Lew E. Darve 《International journal for numerical methods in engineering》2011,85(5):640-669
Recently, graphics processing units (GPUs) have had great success in accelerating many numerical computations. We present their application to computations on unstructured meshes such as those in finite element methods. Multiple approaches in assembling and solving sparse linear systems with NVIDIA GPUs and the Compute Unified Device Architecture (CUDA) are created and analyzed. Multiple strategies for efficient use of global, shared, and local memory, methods to achieve memory coalescing, and optimal choice of parameters are introduced. We find that with appropriate preprocessing and arrangement of support data, the GPU coprocessor using single‐precision arithmetic achieves speedups of 30 or more in comparison to a well optimized double‐precision single core implementation. We also find that the optimal assembly strategy depends on the order of polynomials used in the finite element discretization. Copyright © 2010 John Wiley & Sons, Ltd. 相似文献
10.
Voronoi图栅格生成算法GPU并行实现 总被引:1,自引:0,他引:1
针对矢量法生成Voronoi图计算与存储复杂的缺点,重点分析研究了Voronoi图的栅格生成方法。对不同的栅格生成算法的复杂性和效率进行了比较分析,并针对以往方法速度较慢的问题,提出一种CUDA平台下GPU并行栅格扫描的方法。该方法利用GPU的多线程特性,将各个栅格的计算分散到不同的线程中并行处理。相比其他栅格生成方法,该方法不需要考虑栅格的规模,能够以几乎线性的时间完成Voronoi图的生成,极大地提高了生成速度。 相似文献