A novel low-latency DRAM based on the bitline-discharge rate

As well known by computer architects, the performance gap between the processor and the memory has been increasing over the years. This causes what is known as the memory wall. In order to alleviate the problem, a novel fast readout scheme is proposed in this article for the single-transistor single-capacitor dynamic random-access memory (1T-1C DRAM) cells. The proposed scheme works in the current domain in which the difference between the discharging rates of the bitline in the cases of ‘1’ and ‘0’ readings is detected. The proposed scheme is analysed quantitatively and compared with the conventional readout scheme. It is verified by simulation adopting the 45 nm CMOS Berkley predictive-technology model (BPTM) and shows 44 and 7.7% reductions in the average read-access and cycle times, respectively, as compared to the conventional readout scheme. It is also shown that the power is saved according to the proposed scheme if the probability of occurrence of ‘0’ storage exceeds 66.7%. This minimum value can be alleviated, however, at the expense of a smaller saving in the average read-access time. The impacts of process variations and technology scaling are also taken into account.     

Fully Programmable Memory BIST for Commodity DRAMs

To accomplish a high‐speed test on low‐speed automatic test equipment (ATE), a new instruction‐based fully programmable memory built‐in self‐test (BIST) is proposed. The proposed memory BIST generates a high‐speed internal clock signal by multiplying an external low‐speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on‐the‐fly to perform complicated and hard‐to‐implement functions, such as loop operations and refresh‐interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.     

用8031，DRAM和高速A/D实现快速数据采集

介绍了一个用８０３１，ＤＲＡＭ和高速Ａ／Ｄ等芯片构成的快速数据采集系统。该系统使Ａ／Ｄ转换的数据不经ＣＰＵ“中转”，而直接存入ＤＲＡＭ中。它具有硬件结构简单、价格低廉、易实现大容量存储等优点。本系统对模拟信号的采集并将采集数据送入存储器的周期为８μｓ。     

基于DSP的伺服运动控制器

为满足高准确度自动化数控加工的要求,以微机接口和电机伺服控制技术为基础,提出了一种以DSP为控制系统的核心、专用运动控制处理器LM628,和双口RAM为支撑单元的伺服控制系统,给出了该系统功能、硬件结构和软件设计方法．实验证明,该控制器不仅可以方便地实现人机交互和实时控制部件的参数化,而且具有行程轨迹精确、响应速度快、定位准确度高、性能稳定、调速性能好等特性．     

Structure and property changes of ZrO2/Al2O3/ZrO2 laminate induced by low-temperature NH3 annealing applicable to metal-insulator-metal capacitor

Phase transformation and morphology evolution of ZrO₂/Al₂O₃/ZrO₂ laminate induced by the post-deposition NH₃ annealing at 480 °C were studied and the effect on the electrical property of the TiN/ZrO₂/Al₂O₃/ZrO₂/TiN capacitor module was evaluated in dynamic random access memory cell. Experimental results indicated N could indeed be incorporated into the dielectric laminate by the low-temperature NH₃ annealing, resulting in tetragonal-to-cubic phase transformation and small crystallites in the ZrO₂ layers. The C residue and Cl impurity in the ZrO₂/Al₂O₃/ZrO₂ laminate, which derived from the dielectric film formation and capping TiN layer deposition, respectively, could also be reduced by the nitridation process. As a result of the better surface morphology and less impurity content, lower dielectric leakage current and longer reliability lifetime were observed for the nitrided ZrO₂/Al₂O₃/ZrO₂ capacitor. This study demonstrates the low-temperature NH₃ annealing on ZrO₂/Al₂O₃/ZrO₂ dielectric can be applicable to the metal-insulator-metal capacitor structure with nitride-based electrode, which brings advantages over mass production-wise property improvements and extends the practical applicability of the ZrO₂/Al₂O₃/ZrO₂ dielectric.     

A 6 Gbps/pin Low‐Power Half‐Duplex Active Cross‐Coupled LVDS Transceiver with Switched Termination

A novel linear switched termination active cross‐coupled low‐voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross‐coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared preamplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak‐to‐peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.     

炉管制程工艺中的片数效应及其优化方案

随着半导体技术的发展,越来越多的立式炉管在200mm及300mm集成电路晶圆制造中被应用到。同时炉管制程中的片数效应随着集成电路芯片的集成度越来越高而被凸显出来。文章将以LPCVD氮化硅在0.16μm、64M堆叠式内存制造过程中的片数效应为例,阐述炉管制程工艺中的片数效应以及通过调整制程参数（温度、沉积时间）的方式予以解决的实例。文中通过调整炉管上中下的温度来补偿气体的分布不均匀,调整沉积时间来补偿不同片数的沉积速率的差异,两者结合并辅以基于片数的分片程式来解氮化硅电介质沉积的片数效应。同时以此为基础总结出炉管片数效应的解决方案。     

Characterization of energy use in 300 mm DRAM (Dynamic Random Access Memory) wafer fabrication plants (fabs) in Taiwan

Driven by technology advances and demand for enhanced productivity, migration of wafer fabrication for DRAM (Dynamic Random Access Memory) toward increased wafer size has become the fast-growing trend in semiconductor industry. Taiwan accounts for about 18% of the total DRAM wafer production in the world. The energy use required for operating wafer fabrication plants (fabs) is intensive and has become one of the major concerns to production power reliability in the island. This paper characterizes the energy use in four 300 mm DRAM wafer fabs in Taiwan through performing surveys and on-site measurements. Specifically, the objectives of this study are to characterize the electric energy consumption and production of 300 mm DRAM fabs by using various performance metrics, including PEI ((production efficiency index), annual electric power consumption normalized by annual produced wafer area) and EUI ((electrical utilization index), annual electric power consumption normalized by UOP (units of production), which is defined as the product of annual produced wafer area and the average number of mask layers of a wafer). The results show that the PEI and EUI values are 0.743 kWh/cm² and 0.0272 kWh/UOP, respectively. Using EUI in assessing energy efficiency of the fab production provides more consistent comparisons than using PEI alone.     

动态随机存储器栅极侧壁硅化钨残留的去除工艺

动态随机存储器栅极侧壁硅化钨残留造成的短路成为制约提高产品良率及可靠性的瓶颈.为此,采用X射线荧光光谱（XRF）、扫描电镜（SEM）等检测分析手段优化硅/钨原子组成比为2.45.透射电镜（TEM）及电性参数测试结果表明,经30s、1000℃快速热处理可获得方块阻值为12Ω/cm^2的硅化钨,且可刻蚀性能好.在硅化钨刻蚀前利用电子束扫描发现,15min的氢氟酸和10min浓硫酸与过氧化氢混合溶液（SPM）在300W超声波条件下的新湿法清洗工艺,能去除84.7%的表面微粒及残留聚合物.整合上述优化工艺可以将硅化钨残留造成的65nm动态随机存储器芯片失效率由31.3%降到1.9%,为研究下一代产品提供有效借鉴.     

利用FPGA实现SDRAM控制器的设计

介绍了SDRAM的工作原理和使用方法.以一个数据通信中实际使用的SDRAM控制器为例,设计了用可编程逻辑器件(FPGA)实现SDRAM控制器的方法,给出了具体实现时需要注意的地方.