软件工程在电梯控制系统中的实现方法

将软件工程的方法应用到电梯控制系统中．使电梯控制系统具备可观察性．可控制性和可测试性，从而提高电梯控制系统的稳定性和可靠性。     

Automatic Verification of a Behavioural Subset of UML Statechart Diagrams Using the SPIN Model-checker

Statechart Diagrams provide a graphical notation for describing dynamic aspects of system behaviour within the Unified Modelling Language (UML). In this paper we present a translation from a subset of UML Statechart Diagrams - covering essential aspects of both concurrent behaviour, like sequentialisation, parallelism, non-determinism and priority, and state refinement - into PROMELA, the specification language of the SPIN model checker. SPIN is one of the most advanced analysis and verification tools available nowadays. Our translation allows for the automatic verification of UML Statechart Diagrams. The translation is simple, proven correct, and promising in terms of state space representation efficiency. Received September 1999 / Accepted in revised form February 2000     

协同设计中基于状态图的工作流表示模型*

着重讨论了CAD协同设计工作流管理中的工作流表示模型,提出了运用状态图的形式来表示工作流的模型,并详细描述了其定义、特性、建模方法及特性分析,并将该思想应用于建筑协同设计的工作流管理中。     

An algorithm for blob hierarchy layout

Published online: 15 March 2002     

Livechart：一种用于活动性验证的Statechart

Ｌｉｖｅｃｈａｒｔ是地Ｓｔａｔｅｃｈａｒｔ的扩展，它可用于并发系统活动性的验证，并具有直观和严格的特点。它既可以方便地表达用户的直觉又具有严格的语义，因此它在用户的直觉和形式证明之间建立了一个的接口。本文给出了Ｌｉｖｅｃｈａｒｔ的语久和用Ｌｉｖｅｃｈａｒｔ进行活动性验证的方法。     

状态图中基于事件约束的测试路径覆盖策略

提出了一个在状态图中基于事件约束的测试路径覆盖策略，介绍了具有超态的状态图模型，定义了事件约束机制(S-CSPE)，在此约束机制上给出了测试路径覆盖策略。最后给出了该策略与CSPE约束覆盖策略和Rapps-Weyuker路径覆盖标准的比较结果。     

UML状态机模型元素的RSL形式化定义

UML状态机作为UML动态描述机制的重要组成部分,在描述系统及模型的动态行为时扮演着重要的角色,但已有的UML动态语义缺乏准确的形式化描述。首先将UML状态机抽象成图;再将图通过传统的有穷自动机进行语义扩展,同时增加状态分层,形成一个基于UML状态机的有穷自动机;然后用RAISE规约语言RSL对扩展后的自动机进行形式化定义,使UML状态机中的模型元素的语义更加清晰、精确,为后期的UML状态机的操作语义形式化研究打下基础。     

基于Spin的UML状态图模型检查的设计与实现

UML已经是软件建模方面的标准语言,UML Statechart描述了系统在其生命周期中的动态行为。随着系统规模的扩大和复杂度的提高,Statechart往往包含设计者所未预料到的隐患,通过模型检查来对Statechart进行穷举检验就成为一个重要课题,首先给出了含层次、并发Statechart的语义;随后提出了对Statechart进行模型检查的一种新方法,并且已经编写软件SC2Spin实现此方法,该方法使用了提出的Statechart山脉算法和迁移提取法,可以将一个Statechart自动转化为Spin的输入语言Promela,从而验证Statechart的死锁、活锁等错误和时序逻辑公式。     

Using a process algebra interface for verification and validation of UML statecharts

UML diagrams are the conventional methods for visual modeling systems. Among them, the Statechart diagrams are used to show the runtime behavior of a system, but the correctness of such diagrams is the primary concern of the designers because of concurrency issues like livelock, inaccessible states, and non-deterministic states. Process algebra methods have the capabilities that are suitable for verification and validation of Statecharts. To this end, in this paper, process algebra language LOTOS (Language Of Temporal Ordering Specification) is used as the target language, and a method is presented to map UML Statecharts to the LOTOS processes, called USLP. Then the correctness of the proposed mappings is proved by demonstrating the isomorphism relation between the Labeled Transition System (LTS) of a Statechart and the LTS of its transformed LOTOS specification. Next, tools CADP (Construction and Analysis of Distributed Processes) is used for verification and validation of the mapped LOTOS models, and the CSP process algebra and its tools, FDR are used to verify the properties could not be verified by the LOTOS and its toolset. The experimental results show our approach can: (1) verify some properties (the issues) that are not verified by other approaches and (2) reduce the space that should be searched to verify the properties.