南水北调中线总干渠藻类的生态调度

南水北调中线总干渠无在线调蓄水库,对藻类生态调度过程中出现的问题开展生态调度实现策略和实施方式研究。主要实现策略包括:划定自身的调蓄区,隔离生态调度对下游的影响;采用高效的渠池运行方式,减少生态调度时蓄量的反复调整;综合考虑安全、快速、平稳等需求,设定生态调度实施进程和方式。具体实施方式包括:将总干渠划分为流速调控区、调蓄区和正常运行区,分别实施等体积、控制蓄量和闸前常水位方式运行;将生态调度过程划分为充水阶段和泄水阶段,基于流速调控目标值、持续时长和水位降幅约束条件,确定各阶段时长和各分区的闸门群调控方案等。基于2018年3月输水工况,采用明渠一维非恒定流模型,仿真总干渠上游15个渠池的藻类生态调度过程。结果表明,生态调度可在3.5 d内完成,各渠池的平均流速由0.48 m/s增至0.93 m/s,持续时间超过2 h。在整个生态调度过程中,水位变化平稳,水位变幅符合安全阈值要求,下游渠道的正常运行未受生态调度明显影响。     

All two-input logic gates by a single-stage single electron box

In this paper, the design of all two-input logic gates is presented by only a single-stage single electron box (SEB) for the first time. All gates are constructed based on a same circuit. We have used unique periodic characteristics of SEB to design these gates and present all two-input logic gates (monotonic/non-monotonic, symmetric/non-symmetric) by a single-stage design. In conventional monotonic devices, such as MOSFETs, implementing non-monotonic logic gates such as XOR and XNOR is impossible by only a single-stage design, and a multistage design is required which leads to more complexity, higher power consumption and less speed of the gates. We present qualitative design at first and then detailed designs are investigated and optimised by using our previous works. All designs are verified by a single electron simulator which shows correct operation of the gates.     

Discharge coefficient for vertical sluice gate under submerged condition using contraction and energy loss coefficients

A novel method is suggested for the determination of flow discharge in vertical sluice gates with considerably small bias. First, in order to derive an equation for the discharge coefficient, energy-momentum equations are implemented to define the physical realization of the phenomenon. Afterward, the discharge coefficient is presented in terms of contraction and energy loss coefficients. Subsequently, discharge coefficient, contraction, and energy loss coefficients were determined through an implicit optimization technique on the data. Data analysis illustrated that there is a meaningful power relationship between the contraction and energy loss coefficients. Thereafter, dimensional analysis is performed and an explicit best-fit regression equation is developed for defining the energy loss coefficient. The obtained equations for contraction and energy loss coefficients were then used in the computation of the discharge coefficient and determination of the flow discharge in the vertical sluice gate. The performance of the developed approach is validated against the selected benchmarks existing in the literature.     

基于CFD的含小拍门的闸门过流能力分析

针对含悬挂式小拍门的闸门在运行过程中出现撞击力过大、振动严重等问题,对其流动状况进行了数值模拟计算,对比分析了不同拍门方案下的水力损失系数分布和内部流线。结果表明,拍门开启角度一定流量不同时其水力损失系数保持一致,侧翻式拍门和悬挂式拍门在不同角度下的水力损失系数大体相同;在相同过流面积下,悬挂式拍门在开启角度小于35°的状态下水力损失系数小于侧翻式拍门,而在开启角度大于35°的状态下大于侧翻式拍门;侧翻式拍门结构可减小水力损失,增强闸门启闭过程的稳定性。     

Ferroelectric Exchange Bias Affects Interfacial Electronic States

In polar oxide interfaces phenomena such as superconductivity, magnetism, 1D conductivity, and quantum Hall states can emerge at the polar discontinuity. Combining controllable ferroelectricity at such interfaces can affect the superconducting properties and sheds light on the mutual effects between the polar oxide and the ferroelectric oxide. Here, the interface between the polar oxide LaAlO₃ and the ferroelectric Ca-doped SrTiO₃ is studied by means of electrical transport combined with local imaging of the current flow with the use of scanning a superconducting quantum interference device (SQUID). Anomalous behavior of the interface resistivity is observed at low temperatures. The scanning SQUID maps of the current flow suggest that this behavior originates from an intrinsic bias induced by the polar LaAlO₃ layer. Such intrinsic bias combined with ferroelectricity can constrain the possible structural domain tiling near the interface. The use of this intrinsic bias is recommended as a method of controlling and tuning the initial state of ferroelectric materials by the design of the polar structure. The hysteretic dependence of the normal and the superconducting state properties on gate voltage can be utilized in multifaceted controllable memory devices.     

γ-γ符合测量系统的新型前端读出电路研制

研制了一种新型前端读出电路，用于重离子治癌装置中符合测量原型系统的研究和测试。电路主要包括能量链、时间链和数据处理单元。能量链由截止频率7 MHz的抗混叠滤波器和模数转换器(ADC)组成，形成波形采样电路；时间链由高速比较器构成的定时甄别电路和时间数字转换器（TDC）组成；数据处理单元基于现场可编程门阵列(FPGA)设计实现。电路的线性度优于0.8%，噪声小于0.8 mV（RMS）。配合LaBr3单晶体条测试，能量分辨为4.5%（FWHM），在与LYSO晶体阵列配合测试时，位置映射散点图清晰。该前端读出电路性能优于CAMAC系统，具有较好的实际应用前景。     

拍式浮体闸门充压水封仿真计算研究

为了得到充压伸缩框型水封在不同线荷载下运行时水封背腔所需的充压值及相应的水封变形断面和封头接触属性,首先通过一种非线性近似方法得到各工况下框形水封各段的线压力,将三维问题转化为平面问题;然后通过仿真计算求得各充压值下的水封线压力和变形属性,反过来便是所求结果。计算结果表明,拍门充压水封较传统挤压水封在中低水头(一般水头)下具有更好的封水性能,又因其利于拍门缓冲和人为控制,因此具备较好的应用前景。     

手机保护套模内热切模具设计

针对传统冷流道模具需要人工去除浇注系统凝料和冷切浇口技术效果不佳的现状，以某智能手机保护套为例，设计了具有热切浇口功能的手机保护套模具。首先根据产品搭接侧浇口的结构特点，设计了能够将浇口切除干净，且运动准确的切刀装置，并利用有限元分析方法确立了合适的进刀时间和驱动油缸。然后设计了合理的顶出和冷却机构，保证产品和浇注系统凝料在分离冷却后分别被安全顶出。     

Quantum computation based bundling optimization for combinatorial auction in freight service procurements

Combinatorial auction is a useful trade manner for transportation service procurements in e-marketplaces. To enhance the competition of combinatorial auction, a novel auction mechanism of two-round bidding with bundling optimization is proposed. As the recommended the auction mechanism, the shipper/auctioneer integrates the objects into several bundles based on the bidding results of first round auction. Then, carriers/bidders bid for the object bundles in second round. The bundling optimization is described as a multi-objective model with two criteria on price complementation and combination consistency. A Quantum Evolutionary Algorithm (QEA) with β-based rotation gate and the encoding scheme based on non-zero elements in complementary coefficient matrix is developed for the model solution. Comparing with a Contrast Genetic Algorithm, QEA can achieve better computational performances for small and middle size problems.     

Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization

Accelerated life testing (ALT) of a field programmable gate array (FPGA) requires it to be configured with a circuit that satisfies multiple criteria. Hand-crafting such a circuit is a herculean task as many components of the criteria are orthogonal to each other demanding a complex multivariate optimization. This paper presents an evolutionary algorithm aided by particle swarm optimization methodology to generate synthetic benchmark circuits (SBC) that can be used for ALT of FPGAs. The proposed algorithm was used to generate a SBC for ALT of a commercial FPGA. The generated SBC when compared with a hand-crafted one, demonstrated to be more suitable for ALT, measured in terms of meeting the multiple criteria. The SBC generated by the proposed technique utilizes 8.37% more resources; operates at a maximum frequency which is 40% higher; and has 7.75% higher switching activity than the hand-crafted one reported in the literature. The hand-crafted circuit is very specific to the particular device of that family of FPGAs, whereas the proposed algorithm is device-independent. In addition, it took several man months to hand-craft the SBC, whereas the proposed algorithm took less than half-a-day.