A Scalable Interconnection Network Architecture for Petaflops Computing

Extrapolating technology advances in the near future, a computer architecture capable of petaflops performance will likely be based on a collection of processing nodes interconnected by a high-performance network. One possible organization would consist of thousands of inexpensive, low-power symmetric multiprocessor (SMP) nodes. Each node will inject data into the interconnection network at a very large rate and consequently, the interconnect scheme is one of the most crucial design issues affecting system performance. This paper describes the 2D simultaneous optical multiprocessor exchange bus (2D SOME-Bus) which has the potential to become the basis of a high-end computer architecture capable of petaflops performance. It consists of N horizontal, N vertical 1D SOME-Bus networks, and N ² nodes. Each node is connected to one horizontal and one vertical 1D SOME-Bus. Each of N nodes connected to one 1D SOME-Bus has a dedicated broadcast channel and an input channel interface based on an array of N receivers monitoring all N channels and allowing multiple simultaneous broadcasts. In the 2D SOME-Bus, messages being broadcast on one Bus can be broadcast in a cut-through manner on one or more Buses in the other dimension. This paper describes the optoelectronic devices and technology which make the 2D SOME-Bus possible, and the network interface organization. It also presents simulation results which compare the performance of the 2D SOME-Bus, the 1D SOME-Bus, the crossbar and the torus under the message-passing paradigm.     

Challenges and possible approaches: towards the petaflops computers

Roadrunner Hardware and Software Overview

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Challenges and possible approaches: towards the petaflops computers

In parallel with the R&D efforts in USA and Europe, China’s National High-tech R&D program has setup its goal in developing petaflops computers. Researchers and engineers world-wide are looking for appropriate methods and technologies to achieve the petaflops computer system. Based on discussion on important design issues in developing the petaflops computer, this paper raises the major technological challenges including the memory wall, low power system design, interconnects, and programming support, etc. Current efforts in addressing some of these challenges and in pursuing possible solutions for developing the petaflops systems are presented. Several existing systems are briefly introduced as examples, including Roadrunner, Cray XT5 jaguar, Dawning 5000A/6000, and Lenovo DeepComp 7000. Architectures proposed by Chinese researchers for implementing the petaflops computer are also introduced. Advantages of the architecture as well as the difficulties in its implementation are discussed. Finally, future research direction in development of high productivity computing systems is discussed.     

MilkyWay-2 supercomputer: system and application

On June 17, 2013, MilkyWay-2 (Tianhe-2) supercomputer was crowned as the fastest supercomputer in the world on the 41th TOP500 list. This paper provides an overview of the MilkyWay-2 project and describes the design of hardware and software systems. The key architecture features of MilkyWay-2 are highlighted, including neo-heterogeneous compute nodes integrating commodity-off-the-shelf processors and accelerators that share similar instruction set architecture, powerful networks that employ proprietary interconnection chips to support the massively parallel message-passing communications, proprietary 16-core processor designed for scientific computing, efficient software stacks that provide high performance file system, emerging programming model for heterogeneous systems, and intelligent system administration. We perform extensive evaluation with wide-ranging applications from LINPACK and Graph500 benchmarks to massively parallel software deployed in the system.     

HPP:一种支持高性能和效用计算的体系结构

为了同时做到应对千万亿次高性能计算的技术挑战和满足数据中心(data center)未来的主要应用模式效用计算(utility computing)的需求,提出了一种称为HPP(Hyper Parallel Processing)的高性能计算机体系结构.HPP的主要特征是全局地址空间(global address space)和单一操作系统映像的超节点(hyper node).HPP结合了MPP的可扩展性,DSM的高效通信和机群的普及化的优点,为高性能计算和效用计算都提供了许多创新研究的机会.基于HPP体系结构,实现了一个曙光5000高性能计算机的原型系统,初步验证了它的可行性.