一种高性能数字下变频硬件计算结构

数字下变频是软件无线电的核心技术,随着通信技术的发展,如今对其处理速度要求越来越高。现提出了一种高性能的数字下变频硬件计算结构,使用CORDIC,流水线划分,重定时等技术来优化数字下变频各个模块的硬件结构。通过和传统设计方案的实验比较,证明了本方案能在将FPGA总体资源使用等效门数减少29．54％的情况下,将最高数据吞吐率提升6．74倍。     

FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm

This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow retiming can break the critical path of the design into finer pieces to improve the throughput of the design. The complexity of the C-slow retiming on FPGA is to find the best register allocation in the data path of the design so that by increasing the number of registers, relocation of the registers to balance the AES architecture be in the best mode, and the critical path be optimally pipelined and improved. In this paper, architecture of the AES algorithm is implemented in the gate level by high-speed and breakable structures that are desirable for the 2-slow retiming. The Mix-columns transformation is implemented based on multiplication by constants 2 and 3 modules with combinational logic circuits. This work has been successfully verified and synthesized using Xilinx ISE 11 byVirtex-5, XC5VLX85 FPGA. The proposed implementation achieves a high throughput of 86 Gb/s and high maximum operation frequency of 671.524 MHz whereas the highest throughput and the highest operation frequency reported in the literature are 73.737 Gb/s and 576.07 MHz, respectively.     

H20-20 IXP2000调度交换系统在SDH设备中的透明延伸

对HARRIS IXP2000调度交换机系统下数字调度台及普通分机远距离传输方案进行了详细的描述。提供了SDH光端机为终端设备在2Mbit/s业务码流中提取同步信号的方法,阐述了E1远端模块的性能特点。     

Design of testable sequential circuits by repositioning flip-flops

This paper presents a technique to enhance the testability of sequential circuits by repositioning flip-flops. A novel retiming for testability technique is proposed that reduces cycle lengths in the dependency graph, converts sequential redundancies into combinational redundancies, and yields retimed circuits that usually require fewer scan flip-flops to break all cycles (except self-loops) as compared to the original circuit. Our technique is based on a new minimum cost flow formulation that simultaneously considers the interactions among all strongly connected components (SCCs) of the circuit graph to minimize the number of flip-flops in the SCCs. A circuit graph has a vertex for every gate, primary input and primary output. If gatea has a fanout to gateb, then the circuit graph has an arc from vertexa to vertexb. Experimental results on several large sequential circuits demonstrate the effectiveness of the proposed retiming for testability technique in reducing the number of partial scan flip-flops.     

An Effective Software Pipelining Algorithm for Clustered Embedded VLIW Processors

This paper proposes a software pipelining framework, CALiBeR (ClusterAware Load Balancing Retiming Algorithm), suitable for compilers targetingclustered embedded VLIW processors. CALiBeR can be used by embedded systemdesigners to explore different code optimization alternatives, that is, high-qualitycustomized retiming solutions for desired throughput and program memory sizerequirements, while minimizing register pressure. An extensive set of experimentalresults is presented, demonstrating that our algorithm compares favorablywith one of the best state-of-the-art algorithms, achieving up to 50% improvementin performance and up to 47% improvement in register requirements. In orderto empirically assess the effectiveness of clustering for high ILP applications,additional experiments are presented contrasting the performance achievedby software pipelined kernels executing on clustered and on centralized machines.     

Variables Bounding Based Retiming Algorithm

Retiming is a technique for optimizing sequential circuits.In this paper,we discuss this problem and propose an improved retiming algorithm based on varialbes bounding.Through the computation of the lower and upper bounds on variables,the algorithm can significantly reduce the number of constratints and speed up the execution of retiming.Furthermore,the elements of matrixes D and W are computed in a demand-driven way,which can reduce the capacity of memory,It is shown through the experimental results on ISCAS89 benchmarks that our algorithm is very effective for large-scale seuqential circuits.     

基于FPGA的高速自适应滤波器的实现

在LMS算法进行变步长处理的基础上,结合驰豫超前流水线技术和时序重构技术提出了创新结构和改进算法,在FPGA的仿真综合环境中设计实现了该高速自适应滤波器,并且在AlteraDE2-70开发板上进行了板级测试。     

Loop Shifting for Loop Compaction

The idea of decomposed software pipelining is to decouple the software pipelining problem into a cyclic scheduling problem without resource constraints and an acyclic scheduling problem with resource constraints. In terms of loop transformation and code motion, the technique can be formulated as a combination of loop shifting and loop compaction. Loop shifting amounts to moving statements between iterations thereby changing some loop independent dependences into loop carried dependences and vice versa. Then, loop compaction schedules the body of the loop considering only loop independent dependences, but taking into account the details of the target architecture. In this paper, we show how loop shifting can be optimized so as to minimize both the length of the critical path and the number of dependences for loop compaction. The first problem is well-known and can be solved by an algorithm due to Leiserson and Saxe. We show that the second optimization (and the combination with the first one) is also polynomially solvable with a fast graph algorithm, variant of minimum-cost flow algorithms. Finally, we analyze the improvements obtained on loop compaction by experiments on random graphs.     

关于再定时对于E1时钟传送性能影响的测试及分析

阐述了SDH的E1支路"再定时"功能,指出目前业内基本不采用的现实情况,并通过实际测试验证"再定时"对于提高时钟信号质量的效果,详细介绍了测试的步骤和方法,并提出明确的建议。