The role of electron trap creation in enhanced hot-carrierdegradation during AC stress [n-channel MOSFET]

Enhanced AC degradation during gate voltage transients is shown to be related to neutral electron traps created at low gate voltages under conditions of hole injection and filled at high gate voltages under conditions of electron injection. During DC stress, where interface state damage dominates, electron trap damage is not seen because the created traps are neutral. In experiments where inductive ringing is eliminated, AC degradation rates are independent of the type of edge (falling versus rising) and independent of the rise/fall time