A comprehensive study of performance and reliability of P, As, andhybrid As/P nLDD junctions for deep-submicron CMOS logic technology |
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| Authors: | Nayak D.K. Ming-Yin Hao Umali J. Rakkhit R. |
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| Affiliation: | Logic Technol. Div., Adv. Micro Devices Inc., Sunnyvale, CA; |
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| Abstract: | A comprehensive study of P, As, and hybrid As/P nLDD junctions is presented in terms of performance, reliability, and manufacturability for the first time. It is found that As junctions limit the performance of deep submicron devices due to unacceptable hot-carrier reliability, whereas a hybrid junction (light dose P added to medium dose As) dramatically improves hot-carrier reliability while maintaining high performance and manufacturability. For Leff of 0.19 μm, using this hybrid junction in a manufacturing process, an inverter gate delay of 32 ps, dc hot carrier life time exceeding ten years, and off-state leakage below 30 pA/μm at 2.9 V have been achieved |
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