Sample preparation techniques for physical analysis of VLSIs |
| |
| Authors: | S Nakajima S Nakamura T Ueki T Sakai |
| |
| Affiliation: | a Solid-State Analysis Center, Electronics Business Group, NTT Electronics Corporation, 3-1 Morinosato-Wakamiya, Atsugi-shi, Kanagawa Pref., 243-0198, Japan;b Department of Information Processing, Tokyo Institute of Technology, Japan |
| |
| Abstract: | A sample preparation machine introduces a variety of techniques for low-damage sample preparation, especially for the physical analysis of chip size packages (CSPs) and the flip-chip. The techniques are not only useful for CSPs and the flip-chip, but also for a variety of single components. Sample preparation time is greatly reduced. |
| |
| Keywords: | |
| 本文献已被 ScienceDirect 等数据库收录！ |
|
