信号反弹作用下的3D-SIC过硅通孔测试结构

三维堆叠集成电路(3D-SIC)主要采用过硅通孔(through silicon via,TSV)技术来实现电路在垂直方向上的互连,但TSV在制造过程或绑定后阶段都有可能出现失效,导致整个芯片无法正常工作。针对通过TSV绑定后的3D芯片,利用信号在导体中传输的不可逆性,在测试信号发送端施加两次不同测试激励,在其他层的测试信号接收端增加反弹模块,再利用触发器和多路选择器将两次反馈结果进行比较,实现针对TSV的测试。实验结果表明,180nm CMOS工艺下,与同类方法比较,提出的测试结构面积和测试平均功耗分别减少59.8%和18.4%,仅仅需要12个测试时钟周期。有效地证明了结构具有面积和时间开销较小,功耗较低的特性。

Test architecture for through silicon vias in 3D-SIC under signal rebounding

Multiple dies are mainly stacked by Through Silicon Vias（TSVs）,which are called three dimensional Stacked Integrated Circuit（3D-SIC）,but TSVs might be appear some defects during the fabrication or post bond stage,which causes that the entire chip does not work.This paper presents a kind of rebounding module which aims at comparing one value from the signal sender with the other value from the signal receiver based on using the irreversibility of the signal transmission conductor after post-bond stage and utilizes the trigger and multi-selector to compare the results of two feedback.In 180nm CMOS process.The experimental results show that the test architecture area and the test average power consumption decreased by 59.8% and 18.4% compared with the other method,and this architecture only needs 12 test clock cycle.It effectively proves that the architecture has a smaller area and time overhead,lower power consumption characteristics.