A tunable CMOS Wilkinson power divider using active inductors

This paper presents the design and implementation of a tunable CMOS Wilkinson power divider using active inductors. Compared to a conventional active inductor topology, the proposed active inductor features higher inductance tuning range, higher self-resonant frequency, and lower power consumption by introducing two additional transistors. Benefitting from the superior inductor, the low-loss Wilkinson power divider is practical while maintaining a wide tuning range. The design consuming 10.2 mW demonstrates an insertion loss of 0.67 dB, a return loss of 27 dB, and an isolation of 22.6 dB at 8 GHz. Moreover, the tuning range of the circuit is between 5.8 GHz and 10.4 GHz, rendering a 4.6 GHz bandwidth. The active chip size of the lumped design is merely 0.25 mm × 0.15 mm.