An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies |
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| Affiliation: | 1. School of Materials Science and Engineering, Nanyang Technological University, Singapore 639798, Singapore;2. CNES, French Space Agency, 18 Avenue Edouard Belin, Toulouse 31401, France;3. Temasek Laboratories@NTU, Nanyang Technological University, Singapore 637553, Singapore;1. Department of Mechanical Engineering, Nan Kai University of Technology, Taiwan;2. Graduate Institute of Precision Engineering, National Chung Hsing University, Taichung 402, Taiwan;1. School of Aeronautic Science and Engineering, Beihang University, Beijing, China;2. Quality Management Branch of China National Institute of Standardization, Beijing, China;3. Beijing Institute of Control Engineering, Beijing, China;1. Department of Electrical and Electronic Engineering, University of Cagliari, Cagliari, Italy;2. Intraspec Technologies, 3 avenue Didier Daurat, 31400 Toulouse, France;3. CNES, 18 avenue Edouard Belin, 31401 Toulouse Cedex 9, France;1. Fraunhofer Institute for Microstructure and Systems IMWS, Halle, Germany;2. ELMOS Semiconductor AG, Dortmund, Germany |
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| Abstract: | Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimating yield in large SRAM arrays. Conventional SRAM variability metrics require including test structures that cannot be used to investigate cell bit fails in functional SRAM arrays. This work proposes the Word Line Voltage Margin (WLVM), defined as the maximum allowed word-line voltage drop during write operations, as a metric for the experimental characterization of write stability of SRAM cells. Their experimental measurement can be attained with minimal design modifications, while achieving good correlation with existing writability metrics. To demonstrate its feasibility, the distribution of WLVM values has been measured in an SRAM prototype implemented in 65 nm CMOS technology. The dependence of the metric with the width of the transistors has been also analysed, demonstrating their utility in post-process write stability characterization. |
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