Giga-hertz rate single slope conversion technique with 512-phase RTWO |
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Authors: | John Wood Ahmet Tekin Adrian Dave Kenneth Pedrotti |
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Affiliation: | 1. Multigig Inc., Scotts Valley, CA, 95066, USA 2. Department of Electrical and Computer Engineering, University of California, Santa Cruz, CA, 95064-1077, USA
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Abstract: | In this paper, an 8-bit 1.2 Gsample/s single-slope ADC architecture is presented. The proposed technique utilizes the picosecond-accurate phases of a rotary traveling wave oscillator (RTWO). The proof-of-concept test chip is fabricated in a 0.18-μm CMOS process and occupies 1.3 mm × 1.3 mm of die area. Power consumption is 36 mW for the core and 135 mW for on-chip clocks. |
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