VHDL语言及其在实际电路设计中的简化问题

VHDL（超高速集成电路硬件描述语言）目前在电子设计领域得到了广泛的应用。但是，实现同样的系统功能，不同的电路设计师可以采用不同的实际方法，这样就存在一个电路复杂程度的问题，因此，有必要深入讨论在VHDL设计设计、应用中如何简化实际电路，达到优化设计的要求。影响电路复杂程度的主要因素有：不同的语言描述方法，逻辑设计的合理性，VHDL语句的运用灵活程度和设计规划的优劣程度，为尽可能简化电路设计，可以采用；避免不必要的寄存器描述，人解逻辑电路以减少占用面积，用集成度高的电路语言直接表述和采用最简单，优化的设计方案。

VHDL and Its Simpled Problem in Actual Circuit Design

VHDL was widely used in electronic design field today. However, to realize the same system function, different circuit designer may adopt different method, there is a problem of complexity in circuits. Therefore, it is essential to study how to predigest actual circuit and achieve optimized design in VHDL. There are some key factors to affect the complexity in circuit: different language design method , rationality in logistic design, use VHDL flexiblely and different design layout. In order to predigest circuit design, it is adopted as follows: avoid unnecessary register design, decompose logistic circuit to reduce occupied area, use direct integrate circuit language and adopt simplest and the most excellent design method.