|
|||||
|
|
| 一种基于分频链的时钟校准方法 | |
| 引用本文： | 严迪超,徐东明,陈文宣.一种基于分频链的时钟校准方法[J].中国集成电路,2011,20(7):67-71. |
| 作者姓名： | 严迪超 徐东明 陈文宣 |
| 作者单位： | 1. 西安邮电学院电子工程学院,陕西西安,710061 2. 西安邮电学院通信与信息工程学院,陕西西安,710061 3. 西安深亚电子有限责任公司,陕西西安,710061 |
| 摘 要： | 针对晶体振荡器的温漂特性,设计了一种基于分频链的时钟校准算法。在不改变晶体振荡器的情况下可调节时钟频率,校准精度达±0.25ppm,校准范围±32ppm,通过多次实验分析,用Verilog-HDL语言编写全部模块,在modelsim6.2b软件中实现模块仿真。全部功能正常实现,符合设计要求。 |
| 关 键 词： | Verilog-HDL 时钟 晶体振荡器 校准 |
A clock calibration algorithm based on divide-chain frequency |
|
| YAN Di-chao,XU Dong-ming,CHEN Wen-xuan.A clock calibration algorithm based on divide-chain frequency[J].China Integrated Circuit,2011,20(7):67-71. | |
| Authors: | YAN Di-chao XU Dong-ming CHEN Wen-xuan |
| Affiliation: | 1.Xi＇an University of Posts and Telcommunications Xi＇an 710061;2.Xi＇an University of Posts and Telcommunications Xi＇an 710061;3.Xi＇an Supermicro Electronics Co.,LTD Xi＇an 710061) |
| Abstract: | A calibration algorithm based on divide-chain frequency is designed for the crystal oscillator temperature drift characters.This algorithm can adjust the clock frequency without changing the crystal oscillator.With this method,the calibration accuracy is ±0.25p pm,and the range of calibration is ±32 ppm.Based on many experiments,all modules are compiled by Verilog HDL language,and the modules are realized with Modelsim 6.2b.All of the functions are successfully realized and the result meet requirements. |
| Keywords: | Verilog-HDL Clock Crystal Oscillator Calibration |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ | |