| 浮点加法器的低功耗结构设计 |
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| 引用本文： | 高海霞,杨银堂. 浮点加法器的低功耗结构设计[J]. 微电子学, 2002, 32(2): 128-130,135 |
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| 作者姓名： | 高海霞 杨银堂 |
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| 作者单位： | 西安电子科技大学,微电子研究所,陕西,西安,710071 |
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| 摘 要： | 浮点加法器是集成电路数据通道中重要的单元，它的性能和功耗极大地影响着处理器和数字信号处理器的性能。文章分析了浮点加法器的几种结构，重点介绍了实现低功耗的三数据通道结构。最后，还对浮点加法器结构的实用性进行了分析。
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| 关 键 词： | 浮点加法器 低功耗 结构设计 数字信号处理器 数据通道 数字集成电路 |
| 文章编号： | 1004-3365(2002)02-0128-03 |
Design of a Low Power Architecture for Floating-Point Adders |
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| GAO Hai xia,YANG Yin tang. Design of a Low Power Architecture for Floating-Point Adders[J]. Microelectronics, 2002, 32(2): 128-130,135 |
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| Authors: | GAO Hai xia YANG Yin tang |
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| Abstract: | Floating point adder is an important block in IC datapaths Its performance and power consumptions have a great effect on the performance of processors and DSP's In this paper, several architectures for floating point adder are summarized and analyzed A low power triple datapath architecture is described in particular Finally, the practicability of floating point adder architecture has been analyzed |
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| Keywords: | Digital signal processor Data path Floating point adder Low power design |
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