基于FPGA的嵌入式CPU的VHDL建模和设计

目前，基于FPGA的嵌入式CPU核的设计已成为SOC设计的重要部分．提出一种嵌入式CPU核的VHDL行为建模方法，与传统的基于电路结构建模的CPU核的设计方法不同，新的VHDL建摸方法是基于指令对数据流流通控制行为的描述．使用这种方法可以快速建创建兼容已有指令集的CPU核的VHDL模型，易于修改，提高设计效率．同时介绍了兼容8051单片机指令的CPU的VHDL设计例子，并给出使用ISE7．1工具在Xilinx的Sparten 3器件上进行综合实现CPU核设计的结果和使用Modesim6．0工具进行指令操作仿真的结果．仿真的结果显示该建模方法是可行的，设计的CPU核可以运行在125MHz时钟工作频率，指令执行速度超过40MIPS．

VHDL designing and modeling method in FPGA-based embedded CPU

The design of embedded CPU is becoming an important part of SOC now. This paper presents a new design concept for embedded CPU design. Instead of conventional design method based on circuit construct, this design method of based on data flow concurrency that can rapidly and efficiently construct the VHDL model of CPU core, which is compatible with other microprocessor at instruct sets. This paper introduces the VHDL design of CPU core, which is compatible with 8051 microprocessor at instruct sets. The implementation of CPU core design is carried on the Sparten 3 with Xilinx with ISE7.1 tool. In addition, the simulation with modelsim 6.0 shows that the CPU core can run at 125 MHz clock frequency and has high performance over 40 MIPS.