基于FPGA的USB3.0通信架构设计与实现

针对USB设备与主机通信存在的带宽瓶颈问题，设计一款基于USB3.0协议的高速通信架构，为嵌入式设备与PC之间的USB数据高速通信提供一种可选方案。本设计采用Cypress的EZ-USB FX3芯片作为USB的外设控制器，以FPGA作为整个硬件系统的主控芯片，通过对FPGA硬件系统进行设计，对设备固件进行设计与调优，该架构支持USB 2.0/3.0接口自适应，能够实现主机、国产嵌入式CPU、SRAM之间的两两可变帧长通信，硬件传输速度达到360 MB/s，数据连续传输速度达到148 MB/s。

Design and Implementation of USB 3.0 Communication Architecture Based on FPGA

In order to solve the problem of bandwidth bottleneck in the communication between USB and host, a high speed communication architecture based on USB3.0 protocol is designed to provide an alternative scheme for USB data communication between embedded devices and PC. This design uses the EZ-USB FX3 chip of Cypress as a USB peripheral controller, FPGA as the main control chip in the hardware system. Through the design of FPGA hardware system, design and optimization of device firmware, the architecture supports USB 2.0/3.0 adaptive interfaces, it can realize the variable frame length communication between host and domestic embedded CPU and SRAM, hardware transmission speed of 360 MB/s, continuous data transmission speeds of up to 148 MB/s.