|
|||||
|
|
| 基于FPGA的前向纠错算法 | |
| 引用本文： | 沈杨豪,李广军. 基于FPGA的前向纠错算法[J]. 国外电子元器件, 2006, 0(2): 36-39 |
| 作者姓名： | 沈杨豪 李广军 |
| 作者单位： | 电子科技大学,通信与信息工程学院,四川,成都,610054 |
| 摘 要： | 研究数字音频无线传输中的前向纠错(FEC)算法的设计及实现,对前向纠错中的主要功能模块,如RS编解码、交织器与解交织器等给出基本算法及基于现场可编程门阵列(FPGA)和硬件描述语言的解决方案.选用硬件描述语言VerilogHDL,在开发工具QuartusⅡ4.2中完成软核的综合、布局布线和汇编,在Modelsim中进行时序仿真验证,最终下载到开发板中进行电路验证及测试. |
| 关 键 词： | RS码 交织 现场可编程门阵列 前向纠错 |
| 文章编号： | 1006-6977(2006)02-0036-04 |
| 修稿时间： | 2005-07-21 |
FPGA implementation of forward error correction |
|
| SHEN Yang-hao,LI Guang-jun. FPGA implementation of forward error correction[J]. International Electronic Elements, 2006, 0(2): 36-39 | |
| Authors: | SHEN Yang-hao LI Guang-jun |
| Abstract: | The arithmetic and the circuit implementation of Forward Error Correction(FEC)in digital audio wireless transmission are researched,the basic arithmetic and solutions based on FPGA and HDL to the key functional modules of FEC,such as RS codec,interleaver,deinterleaver are given.The IP core's synthesis,place route and assemble are based on develop tool QuartusII4.2.The timing simulation is based on Modelsim.At last,the IP is downloaded in develop kit,and the circuit verification and test is done. |
| Keywords: | RS code interleave FPGA forward error correction |
| 本文献已被 CNKI 万方数据 等数据库收录！ | |